Sr. Physical Design Engineer,
Qualcomm
At a glance
AI generatedAs a Senior ASIC Engineer at Qualcomm Technologies, you will join a dynamic team focused on developing high-performance, low-power semiconductor products. Your role involves defining and modeling IP blocks for SoCs, optimizing designs for performance and power efficiency, and verifying them through rigorous testing. You will use tools like RTL to GDS Flow and Virtuoso to execute complex design flows from architecture definition to implementation. Key responsibilities include collaborating with cross-functional teams to develop system-level requirements, creating detailed technical documentation, and evaluating the entire process flow from high-level design to verification. This position requires a Master's degree in Electrical/Electronic Engineering or related fields, along with extensive experience in ASIC design, verification methods, and scripting languages such as Python or Perl.
Skills
What you'll do
What we're looking for
Market check
This $98,500–$147,700 range sits above 18% of similar postings on FindRole.
Peer median band
$126,950–$210,000
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$136,416–$209,125
Middle half of comparable postings.
Based on 238 comparable postings.
* 240 is the maximum number of comparable postings sampled.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 569 open roles on FindRole.
Listed pay typically runs $148,300–$224,400 across 536 roles with salary data.
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