Browse tech roles

C++ SystemVerilog UVM Object-Oriented Programming Python Perl Makefile Git Jenkins Docker Linux Windows CI/CD +8 more Show less

Python SystemVerilog UVM VCS Verdi Jenkins Make CI/CD Perl Docker Kubernetes Terraform AWS GCP Git GitHub Mercurial SVN Prometheus Grafana AI Machine_Learning +17 more Show less

Verilog SysVerilog C++ Python Perl TCL AgenticAI ClaudeCode Cursor CoPilot EDA ASIC Design for Testing Scan ATPG JTAG +11 more Show less

SystemVerilog UVM C++ Python Perl Shell scripting VCS Debussy GDB ASIC verification dynamic memory controllers ddr2 ddr3 ddr4 ddr5 lpddr2 lpddr3 lpddr4 lpddr5 lpddr6 +15 more Show less

SystemVerilog UVM C++ Python Perl Formal Verification Coverage Metrics X-propagation DFT/IST Tegra GPU CI/CD +7 more Show less

Verilog SystemVerilog UVM SVA VCS Perl Tcl Makefiles Python LLMs Agentic AI frameworks VCS-XA Gate Level Simulation Formal Equivalence +9 more Show less

SystemVerilog UVM C++ Python Perl Shell scripting VCS Debussy GDB ASIC verification dynamic memory controllers ddr2 ddr3 ddr4 ddr5 lpddr2 lpddr3 lpddr4 lpddr5 lpddr6 HBM GDDR +17 more Show less

Verilog SystemVerilog Python Perl RTL simulation waveform debug digital design logic design concepts +3 more Show less

SystemVerilog UVM C++ Python PCIe CXL CHI VCS Debussy GDB +5 more Show less

UVM C/C++ Python Perl TCL SVA AXI APB DMA Memory Controllers QSPI UART I2C ASIC verification SoC verification UVM testbenches Constrained random methodology Assertion-based design checks Code coverage Functional coverage Formal test plan documentation AI tools +17 more Show less

SystemVerilog UVM Object-Oriented Programming Constrained Random Sequences Scoreboard Functional Coverage Memory Consistency Models Arbitration Policies Interface Protocols On-Chip Interconnect Caches xbar/Interconnect Fabric AI Tools Verification Methodologies +9 more Show less

Python C++ PyTorch JAX TensorRT LLVM MLIR TVM XLA Type Systems Program Semantics Proof-Based Verification Quantization Operator Fusion Mixed-Precision Graph-Level Optimization +11 more Show less

SystemVerilog UVM C Python HLS FPGA Simulation Regression Coverage CI/CD +5 more Show less

C C++ Rust Git Make CMake CUDA OpenCL SMT SymbolicExecution ModelChecking InteractiveTheoremProving LLMAgents NeurosymbolicApproaches CI/CD +10 more Show less

SystemVerilog UVM Perl Python Assertion-Based Verification Semiformal Verification Test Planning Coverage Closure Debugging Object Oriented Programming CI/CD +6 more Show less

C C++ SystemVerilog UVM Perl Python Verilog VHDL Kubernetes Docker CI/CD Git Jenkins GitHub SV Assertions Coverage Tools Power Estimation Tools SpeedBridges +13 more Show less

SystemVerilog UVM VMM Perl Python C C++ PCIe USB SATA Simulation Debugging CoverageDrivenVerification AssertionBasedVerification +9 more Show less

SystemVerilog UVM VCS Verdi Indago GDB Perl C++ Python CI/CD +5 more Show less

SystemVerilog C++ UVM VCS Debussy GDB Python CI/CD Git Linux ASIC GPU Computer Architecture Digital Design Processor Pipeline Verification +10 more Show less

SystemVerilog UVM Python Perl RTL simulation Hardware emulation FPGA prototyping C-model verification Verification IP Reusable verification components EDA tools CI/CD +7 more Show less