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UVM SystemVerilog Verilog Python C/C++ VCS Verdi GDB HLS DisplayPort HDMI MIPI DSI Functional Coverage Assertion-Based Verification Constrained-Random Stimulus Version Control +11 more Show less

Verilog SystemVerilog Python Perl RTL ASIC Mixed-Signal Design DFT Logic Design Waveform Debug PLL High-Speed Interconnects Simulation Hardware Design Digital Design +10 more Show less

SystemVerilog UVM Constrained-Random Verification Coverage-Driven Verification Python Perl Shell ASIC Verification RTL CHI AXI FPGA Emulation Coherent Interconnects +9 more Show less

CPU Performance Modeling Performance Correlation micro architecture Python C++ Perl ARM A64 x86 Workload Analysis Performance Verification CPU Design Scripting Performance Analysis +8 more Show less

System Verilog UVM VCS Verdi Indago GDB C/C++ Perl Assertion-Based Verification Functional Coverage Random Stimulus ASIC Verification Post-silicon Verification +8 more Show less

System Verilog UVM C++ Object-Oriented Programming ASIC Verification SoC Architecture CPU Verification RTL FPGA Emulation +5 more Show less

System Verilog UVM C++ Python Perl ASIC Verification Formal Verification Constraint Random Verification Logic Design Coverage Metrics DFT IST Object-Oriented Programming X prop +9 more Show less

SystemVerilog UVM C++ VCS Digital Design Computer Architecture Assertion-Based Verification Functional Coverage Random Stimulus GDB Debussy Object-Oriented Programming Processor Pipeline Verification ASIC Verification +9 more Show less

Formal Verification System Verilog Verilog RTL TCL Python Perl CPU Architecture Formal Verification Methodologies Assertions Testplans Scripting Post-silicon Verification +8 more Show less

SystemVerilog UVM ASIC Verification Computer Architecture RTL Assertion-Based Verification Object Oriented Programming Post-Silicon Validation Coverage Closure test bench design AI SFV +7 more Show less

SystemVerilog UVM ASIC Verification Python C/C++ Perl VCS Verdi DFT UPF Machine Learning SoC Functional Coverage Assertion-based Verification GDS +10 more Show less

C++ Python Embedded SW Linux Git Gerrit Jenkins Agile Network Protocols System Debugging Firmware +6 more Show less

Formal Verification SystemVerilog Assertions RTL GPU Architecture Formal Property Verification (FPV) 3D Graphics Hardware DPV C2RTL SEQ RTL2RTL SEQ Coverage Closure Abstraction Techniques +6 more Show less

C++ Python Embedded SW Linux Git Gerrit Jenkins Agile Network Protocols System Debugging HW/FW/SW +6 more Show less

SystemVerilog UVM C C++ Verilog VHDL Python Perl Emulation Power Estimation SpeedBridges DPI Transactors Coverage +8 more Show less

SystemVerilog UVM ASIC Verification VCS GDB RISCV C Firmware Object Oriented Programming Functional Coverage Assertion-Based Verification Memory Coherence High Speed IO Protocols Microcontrollers +9 more Show less

Firmware Development Bare-metal C C++ Python RTL SystemVerilog UVM Verdi Linux Windows OS Silicon Bring-up Pre-silicon Post-silicon High-speed IO Data Structures AI Agents +12 more Show less

System Verilog UVM ASIC Verification C++ C Python Perl VCS Debussy GDB FPGA Post-Silicon Verification RTL DDR LPDDR +10 more Show less

SystemVerilog UVM C C++ ASIC Verification Assertion-Based Verification Python Perl VCS IES GDB Debussy Functional Coverage Object Oriented Programming Memory Management Unit Computer Architecture Semiformal Verification (SFV +12 more Show less

Java JavaScript TypeScript Kafka Apache Flink Spark Streaming Redis Docker Kubernetes LangChain OpenTelemetry Elasticsearch Kibana Logstash Grafana Microservices Data Visualization +12 more Show less