Senior Memory Controller Verification Engineer

Nvidia

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Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Employment: Full-time
Posted: 49 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

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At a glance

TL;DR · Senior Memory Controller Verification Engineer

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The Senior Memory Controller Verification Engineer joins the Tegra SoC Memory Subsystem IP verification team to ensure functional correctness and performance for complex design units. You will partner with design and architecture teams to make implementation choices, craft verification test plans, and maintain regressions. Daily responsibilities include developing verification infrastructure such as testbenches, BFMs, checkers, monitors, and randoms while ensuring code and functional coverage of all RTL. You will also drive performance test plans, enable FPGA and software teams, and participate in post-silicon verification and debug. Required skills include SystemVerilog, UVM methodology, and experience with tools like VCS, Debussy, and GDB. The role focuses on verifying dynamic memory controllers including DDR and LPDDR standards within the context of GPU and AI technology.

Skills

System Verilog UVM ASIC Verification C++ C Python Perl VCS Debussy GDB FPGA Post-Silicon Verification RTL DDR LPDDR

What you'll do

Develop verification infrastructure including testbenches, BFMs, checkers, monitors, and random generators.
Create, review, and drive the execution of test plans for planned features.
Define and drive performance test plans based on specific IP requirements.
Ensure full code and functional coverage of all verified RTL.
Coordinate with FPGA and software teams to ensure comprehensive software testing.
Plan for and participate in post-silicon verification and debugging activities.
Maintain regressions and sign off on functional correctness and performance expectations.

What we're looking for

BS / MS or equivalent experience.
3+ years of ASIC verification experience of complex design units.
Background with System Verilog and UVM based methodology for ASIC verification.
Exposure to design and verification tools such as VCS, Debussy, or GDB.
Strong C/C++ programming experience (preferred).
Prior Design or Verification experience of dynamic memory controllers (preferred).
Scripting knowledge in Python, Perl, or shell (preferred).
Strong debugging, problem solving, and interpersonal skills (preferred).

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