Senior Memory Controller Verification Engineer

Nvidia

Confirmed live 2 days ago High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Posted: 3 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $196k

This role $177k

$125k most similar roles pay here $236k

This role pays less than 58% of similar roles. Most pay $175,000–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $196k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Memory Controller Verification Engineer

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As a Senior Memory Controller Verification Engineer on the Tegra SoC Memory Subsystem IP verification team, you will partner with design and architecture teams to make implementation choices and ensure functional correctness and performance expectations are met. Your daily responsibilities include developing verification infrastructure such as testbenches, BFMs, checkers, monitors, and randoms while driving test plan execution for planned features. You will manage code and functional coverage of RTL, collaborate with FPGA and software teams for testing, and participate in post-silicon verification and debug. The role requires expertise in SystemVerilog, UVM methodology, and tools like VCS or Debussy. Preferred skills include C/C++ programming, scripting in Python, Perl, or shell, and specific experience with dynamic memory controllers such as DDR2 through DDR5 and LPDDR2 through LPDDR6 to solve complex design unit challenges.

Skills

System Verilog UVM VCS C C++ Python Perl Shell ASIC Verification RTL FPGA Debussy GDB DDR LPDDR

What you'll do

Develop verification infrastructure including testbenches, BFMs, checkers, monitors, and random generators.
Create, review, and drive the execution of test plans for planned features.
Define and execute performance test plans based on specific IP requirements.
Ensure full code and functional coverage of all RTL being verified.
Coordinate with FPGA and software teams to ensure comprehensive software testing.
Participate in post-silicon verification and debugging activities.
Partner with design and architecture teams to influence implementation choices.

What we're looking for

BS/MS degree or equivalent experience in engineering.
3+ years of ASIC verification experience for complex design units.
Proficiency with SystemVerilog and UVM based methodology for ASIC verification.
Experience with design and verification tools such as VCS, Debussy, or GDB.
Strong C/C++ programming experience (preferred).
Prior design or verification experience of dynamic memory controllers (preferred).
Scripting knowledge in Python, Perl, or shell (preferred).
Strong debugging, problem solving, and interpersonal skills (preferred).

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