Senior Memory Controller Verification Engineer

Nvidia

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Posted: 16 days ago

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $193k

This role $177k

$126k most similar roles pay here $228k

This role pays more than 52% of similar roles. Most pay $169,000–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior Memory Controller Verification Engineer

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NVIDIA is hiring a Senior Verification Engineer for its Tegra SoC Memory Subsystem IP verification team, where you will collaborate with design and architecture teams to develop verification infrastructure, execute test plans, ensure code and functional coverage, and work on post-silicon verification. You will contribute to multiple product lines including consumer graphics, self-driving cars, HPC, cloud computing, and AI. The role requires experience in ASIC verification of complex designs using System Verilog and UVM methodology, along with strong C/C++ programming skills and familiarity with design tools like VCS and debug tools such as Debussy and GDB. Additionally, you should have a background in dynamic memory controllers and scripting knowledge in Python, Perl, or shell, alongside excellent problem-solving and teamwork abilities.

Skills

SystemVerilog UVM C++ Python Perl Shell scripting VCS Debussy GDB ASIC verification dynamic memory controllers ddr2 ddr3 ddr4 ddr5 lpddr2 lpddr3 lpddr4 lpddr5 lpddr6

What you'll do

Develop verification infrastructure including testbenches, BFMs, checkers, monitors, and randoms.
Create and execute detailed test plans for planned features and performance requirements.
Ensure comprehensive code and functional coverage for all RTL being verified.
Collaborate with FPGA and software teams to integrate and test software components.
Plan and participate in post-silicon verification and debugging activities.

What we're looking for

3+ years of ASIC verification experience with complex design units
Proficiency in System Verilog and UVM methodology for verification
Strong C/C++ programming and scripting knowledge (Python/Perl/shell)
Experience verifying dynamic memory controllers (DDR/LPDDR variants)
Ability to develop and maintain verification infrastructure and test plans
Excellent debugging skills and teamwork in a global environment

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