Senior Staff Formal Verification Engineer

Qualcomm

Quick summary

Work type: On-site
Location: San Diego, CA · Santa Clara, CA · Austin, TX
Salary: $195,200–$325,000 / yr
Posted: 145 days ago
Closes: Jul 11, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k

This role $260k

$121k most similar roles pay here $347k

This role pays more than 95% of similar roles. Most pay $163,500–$222,000 — the shaded band above. At the midpoint, this role pays about $260k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 558 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 401 roles with salary data.

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At a glance

TL;DR · Senior Staff Formal Verification Engineer

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The Senior Formal Verification Engineer role at Qualcomm Technologies, Inc.'s Digital ASIC design team involves developing high-quality formal verification test benches to verify complex GPU designs. Day-to-day responsibilities include collaborating with design and implementation teams to ensure thorough verification of hardware components using advanced debugging techniques and formal tools such as Veloce, Palladium, and Zebu emulators. The ideal candidate will have hands-on experience in emulation/simulation acceleration, FPGA systems, and system-level RTL simulation, along with expertise in Verilog/SystemVerilog and knowledge of GPU/CPU/DDR/Bus architectures. Proficiency in C++, Python, Tcl, or Perl scripting is also essential for driving debug failures on emulators and supporting chip bring-up and post-silicon debugging efforts.

Skills

Verilog SystemVerilog UVM Python Tcl Perl C++ Veloce Palladium ZeBu FPGA Xilinx Altera RTL Design Validation Post-Silicon Debug In-Circuit Emulation Simulation Acceleration

What you'll do

Develop high-quality formal verification test benches for complex GPU designs.
Synthesize Verilog RTL and compile models to hardware emulators like Veloce/Palladium/Zebu.
Drive debug failures on emulator using latest technologies; collaborate with designers and SW teams.
Optimize area/performance of synthesized FPGA RTL by working with tool vendors and methodologies.
Support chip bring-up and conduct post-silicon debugging for functional and timing issues.

What we're looking for

Proficient in formal verification methodologies and processes.
Experience with hardware emulator platforms like Palladium, ZeBu, Veloce.
Hands-on experience in emulation/simulation acceleration/FPGA systems.
Strong debugging skills for design validation and post-silicon debug.
Knowledge of Verilog/SystemVerilog and scripting languages (Python, Tcl).
Ability to work closely with design, implementation teams on complex projects.

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