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ASIC FPGA Verilog HDL VHDL Python Tcl Schematic Capture Hardware Bring-up Ethernet PCIe I2C SPI DRAM Signal Integrity DFT +10 more Show less

ASIC DFT Post-Silicon Validation Verilog VCS Gate Level Simulation ATE Patterns P1687 Static Timing Analysis DFT CAD Hardware Bring-up IP Integration Test Architecture Methodology Infrastructure +10 more Show less

Python LLMs LangChain LangGraph AutoGen MCP A2A AGENTS.md Machine Learning open-source Networking Security +7 more Show less

Python SQL Go Java Node.js Rust Snowflake Databricks BigQuery AWS Redshift Apache Kafka PostgreSQL MySQL NoSQL GraphQL REST CI/CD Jenkins GitHub Actions OpenTelemetry Datadog Prometheus S3 GCS CDC ETL ELT +22 more Show less

DFM/DFx Statistical Process Control Design of Experiments Six Sigma Python Machine Learning JMP Spotfire DFT Semiconductor Fabrication Wafer Sort Advanced Packaging Silicon Photonics mmWave DSP Root-Cause Analysis +11 more Show less

C C++ Python SONiC SAI SDK TCP/IP Ethernet L2/L3 Networking Agile JIRA Confluence Distributed Computing Network OS CCNA CCNP CCIE +12 more Show less

Kubernetes Python Go Terraform Ansible Linux AI/ML GPU Clusters SRE infrastructure-as-code Networking Storage Observability Agile +9 more Show less

Python Machine Learning TensorFlow PyTorch Scikit-learn XGBoost Pandas AI Agents AWS GCP Azure Tableau Power BI Matplotlib Seaborn Optuna Time-series Forecasting Anomaly Detection +13 more Show less

Verilog System Verilog DFT MBIST AMBA AXI APB AHB JTAG UPF Formal Verification Linting CDC Checkers Synthesis Post-Silicon Debug RTL +11 more Show less

ASIC DFT Verilog System Verilog Python TCL Perl Synopsys DesignWare SMS TestMax Mentor Graphics Tessent SRAM DRAM Memory Architectures +8 more Show less

DFT CAD Python Tcl Perl Shell Scripting LSF Synopsys TestMAX Synopsys VCS Siemen's Tessent AI ML Pandas STIL ATPG RTL SoC Integration +12 more Show less

Java Spring Boot Kubernetes Docker Kafka MongoDB Cassandra Elasticsearch CI/CD Jenkins Git Spinnaker RAG AI/ML Cloud-native Distributed Systems +11 more Show less

FPGA Verilog HDL VHDL Python Tcl ASIC Schematic Capture Ethernet PCIe I2C SPI MDC/MDIO DRAM Signal Integrity Hardware Bring-up +10 more Show less

DfX NPI ASIC Signal Integrity SI/PI Digital Systems Design Product Development Lifecycle Manufacturing Process Enablement Data Center Networking +4 more Show less

Package Design Signal Integrity Power Integrity High-Speed Routing EDA Tools Python Perl TCL Shell Programming Oscilloscope TDR VNA Silicon Floor Planning Tapeout 2.5D Fanout +10 more Show less

ASIC Package Layout CoWoS SI/PI EDA Tools Cadence APD+ Python Perl TCL high‑speed routing Power Distribution Networks Substrate Layout 2.5D Fanout Floor Planning +9 more Show less

ASIC SoC Physical Design RTL-to-GDSII Floorplanning STA IR/EM PV TCL Python Shell PnR CTS MMMC ECO SDC Mixed-Signal DFT +13 more Show less

Networking Security Cloud AI Infrastructure Routing Switching Wireless VPN Zero Trust Firewall High-Performance Fabrics Hybrid Cloud Telemetry Observability Automation Performance Testing Interoperability Testing +12 more Show less

ASIC Implementation Design-for-Test ATPG Tessent TestMax Tetramax Verilog Gate Level Simulation VCS SDF Scan Insertion JTAG Tcl Python Perl Static Timing Analysis Post-Silicon Validation +12 more Show less

ASIC Package Design Signal Integrity (SI) Power Integrity (PI) High-Speed Routing Power Distribution Networks (PDN) EDA Tools Python Perl TCL Shell Programming Oscilloscopes TDR VNA Silicon Floor Planning Tapeout Hardware Development +11 more Show less