Advanced Packaging Layout Engineering Team Leader, Substrate & Interposer

Cisco

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$214,100–$309,800 / yr
Employment
Full-time
Posted
2 days ago
Freshness
Confirmed live today
Closes
Jan 29, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $203k
This role $262k
$145k $327k
below market most similar roles pay here above market

This role pays more than 94% of similar roles. Most pay $173,781–$231,300 — the blue band above. At the midpoint, this role pays about $262k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 312 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 223 roles with salary data.

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At a glance

TL;DR · Advanced Packaging Layout Engineering Team Leader, Substrate & Interposer

The Advanced Packaging Layout Engineering Team Leader (Substrate & Interposer) joins the Cisco Silicon One team to lead and grow the San Jose layout group. This role involves providing hands-on technical guidance, mentorship, and resource coordination for complex package programs, specifically focusing on advanced ASIC packaging and CoWoS projects. The leader will drive layout activities, optimize package pinouts, stack-ups, power distribution, and escape routing while collaborating with SI/PI teams and manufacturing partners. Key responsibilities include improving methodologies, managing staffing, and ensuring high-quality implementation of high-speed interfaces. Required skills include experience with package layout, power distribution networks, and industry-standard EDA tools like Cadence APD+. Candidates should also possess proficiency in scripting languages such as Python, Perl, or TCL to support engineering efficiency.

What you'll do

  • Lead and provide hands-on technical guidance and mentorship to the San Jose package layout team.
  • Drive package layout activities for complex ASIC advanced packaging and CoWoS projects.
  • Ensure high-quality implementations align with package design, SI/PI, and manufacturing requirements.
  • Coordinate layout resource allocation, priorities, and staffing across multiple concurrent projects.
  • Optimize package pinouts, stack-ups, power distribution, escape routing, and high-speed interface implementation.
  • Partner with global leaders to align methodologies, tools, best practices, and engineering standards.
  • Manage hiring, onboarding, and professional development for layout engineering talent.
  • Drive continuous improvement in layout methodologies, quality, and engineering efficiency.

What we're looking for

  • Must live within commuting distance of the San Jose, CA office and commute 4-5 days per week.
  • Bachelor’s degree in Electrical Engineering with 12+ years of experience, Master’s with 8+ years, or PhD with 5+ years.
  • At least 5 years of experience in package layout or advanced PCB/package implementation.
  • Experience with high-speed routing, power distribution networks (PDN), and package layout design principles.
  • Experience with industry-standard EDA tools for package layout and design.
  • Hands-on experience with Cadence APD+ or equivalent package layout tools.
  • Experience leading or mentoring layout engineers or small technical teams (preferred).
  • Experience with ASIC package substrate layout, CoWoS, SI/PI considerations, and scripting languages like Python, Perl, or TCL (preferred).

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