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Active Keyword: Design Verification Engineer Remove filter Location: Beaverton Remove filter Clear all

3 of up to 20 (filtered)

Design Verification Engineer

Apple Inc

Beaverton, OR 4 days ago
Actively hiring Confirmed live yesterday Posted this week High trust
SystemVerilog UVM Python TCL Perl LLM Gate Level Simulation UPF PCIe USB DDR Formal Verification Emulation RTL Assertion Coverage Collection Waveform Viewers
10+ yrs exp
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CAD Engineer - Design Verification Methodology

Apple Inc

Beaverton, OR 129 days ago
Actively hiring Confirmed live yesterday Low trust
Python TCL Perl Verilog SystemVerilog VHDL VCS Xcelium Modelsim Cadence Synopsys Verdi Indago C C++ Machine Learning RTL
10+ yrs exp
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CAD Engineer - Design Verification Methodology

Apple Inc

Beaverton, OR 152 days ago
Actively hiring Confirmed live yesterday Low trust
Python TCL Perl Verilog SystemVerilog VHDL Synopsys VCS Xcelium Modelsim Verdi Indago C C++ Makefile RTL Machine Learning Artificial Intelligence
3+ yrs exp
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