Browse tech roles

SystemVerilog UVM Python Perl TCL LLM Formal Verification Gate Level Simulation UPF PCIe USB DDR Simulators Waveform Viewers Coverage Collection OOP +11 more Show less

SystemVerilog C C++ Assembly CPU Architecture Digital Logic Design Microarchitecture Post-silicon Bringup RTL Design +4 more Show less

SystemVerilog C C++ Assembly CPU Architecture Digital Logic Design Microarchitecture Post-silicon Bringup RTL Design Transactors +5 more Show less

SystemVerilog UVM Python Perl C++ Assembly Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Digital Simulation Computer Architecture PCI Express DisplayPort MIPI Ethernet TCP/IP NVLink Infiniband Data Structures Algorithms +16 more Show less

SystemVerilog UVM Python Perl C/C++ Assembly Digital Design Computer Architecture Digital Simulation Data Structures Algorithms PCI Express DisplayPort MIPI Hardware Security +10 more Show less

SystemVerilog Verilog Python Perl C++ C Assembly Digital Design Computer Architecture Digital Simulation Debug +6 more Show less

SystemVerilog UVM Digital Simulation Python Perl C/C++ Assembly Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Computer Architecture Digital Design Data Structures Algorithms PCI Express DisplayPort MIPI +13 more Show less

SystemVerilog C C++ Assembly CPU Architecture Digital Logic Design Microarchitecture Post-silicon Bringup RTL Design Transactors +5 more Show less

SystemVerilog C C++ Assembly CPU Architecture Digital Logic Design Microarchitecture Post-silicon Bringup RTL Design +4 more Show less

SystemVerilog UVM Python Perl TCL LLM UPF PCIe USB DDR Formal Verification Gate Level Simulation Simulators Waveform Viewers OOP +10 more Show less

SystemVerilog C C++ Assembly CPU Architecture Digital Logic Design Microarchitecture Post-silicon Bringup RTL Design Transactors +5 more Show less

LVS DRC ANT HVDRC Physical Verification Python Perl Tcl Mentor Calibre Synopsys ICV Tapeout Layout Design Design-for-Manufacturing Design-for-Yield Lithography RDL ESD +12 more Show less

LVS DRC ANT HVDRC ASIC Physical Design Physical Verification Mentor Calibre Synopsys ICV Python Perl Tcl Tapeout Layout Design Design-for-Manufacturing Design-for-Yield Lithography RDL ESD Mixed Signal Back-end Verification +14 more Show less

LVS DRC ANT Physical Verification Layout Design RTL to GDS Mentor Calibre Synopsys ICV Design-for-Manufacturing Design-for-Yield Lithography Padring Bump RDL Scripting Signoff Closure +11 more Show less

Python TCL Perl Verilog SystemVerilog VHDL VCS Xcelium Modelsim Cadence Synopsys Verdi Indago C C++ Machine Learning RTL +12 more Show less