Design Verification Engineer

Apple Inc

Confirmed live today Low trust

Quick summary

Work type
On-site
Location
Beaverton, OR
Posted
40 days ago
Freshness
Confirmed live today

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Salary context

How this pay compares to similar roles

Similar $200k
$141k $242k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $169,625–$230,087.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

As a Design Verification Engineer within the Hardware Technology team, you will ensure the functionality and performance of premier SOCs. You will own the quality of specific IPs or subsystems, such as Neural Engine hardware, DRAM controllers, hardware security, or high-speed IO standards like PCI Express and DisplayPort. Your daily responsibilities include reviewing design and architecture specifications, developing test plans, and defining next-generation verification methodologies and testbenches. You will collaborate with design, architecture, and software teams to identify use cases and corner conditions. Required skills include SystemVerilog, digital simulation, and debug, alongside knowledge of computer architecture and digital design fundamentals. You should also possess proficiency in constrained random verification, functional coverage, assertion methodology, and scripting languages like Python or Perl, while understanding UVM methodologies.

What does a Design Verification Engineer earn?

Median $189224 from 84 postings across 10 companies.

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What you'll do

  • Verify the functionality and performance of Apple’s premier SOCs, IPs, or subsystems.
  • Review design and architecture specifications to ensure quality and performance goals are met.
  • Develop comprehensive test plans, test cases, and coverage plans for hardware designs.
  • Define and implement next-generation verification methodologies and testbenches.
  • Communicate with design, architecture, and software teams to identify use cases and corner conditions.
  • Execute digital verification processes including constrained random verification and assertion methodology.
  • Utilize SystemVerilog, Python, and Perl to perform digital simulation and debugging.

What we're looking for

  • Minimum of a BS degree.
  • Minimum of 10 years of relevant industry experience.
  • Skilled in digital verification including constrained random verification, functional coverage, code coverage, and assertion methodology (preferred).
  • Knowledge of SystemVerilog, digital simulation, and debug (preferred).
  • Knowledge of computer architecture and digital design fundamentals (preferred).
  • Good SW programming skills with knowledge of data structures and algorithms (preferred).
  • Experience with Python, Perl, or similar scripting languages (preferred).
  • Knowledge of verification methodologies like UVM (preferred).

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