Design Verification Engineer

Apple Inc

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Work type: On-site
Location: Beaverton, OR
Posted: 49 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $206k

$139k $253k

below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $169,625–$241,750.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3546 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2746 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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The Design Verification Engineer joins a hardware group to ensure bug-free first silicon for SoC and IP designs. This role involves all phases of pre-silicon verification, including establishing DV methodology, developing test plans based on micro-architecture, and building scalable, portable verification environments. Key responsibilities include creating stimulus, checkers, assertions, and trackers, as well as executing design bring-up, regression enabling, and debugging test failures. The engineer must track progress using various metrics like bugs and coverage. Required technical skills include SystemVerilog, UVM, and Object-Oriented Programming. Candidates should also possess experience with simulators, waveform viewers, build automation, and coverage collection. Proficiency in scripting languages like Python, Perl, or TCL is required, along with the ability to use LLMs to improve verification efficiency and quality.

What does a Design Verification Engineer earn?

Median $191650 from 84 postings across 9 companies.

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Skills

SystemVerilog UVM Python Perl TCL LLM UPF PCIe USB DDR Formal Verification Gate Level Simulation Simulators Waveform Viewers OOP

What you'll do

Study design specifications to create comprehensive test plans for IP features.
Develop verification methodologies and scalable test-benches using SystemVerilog and UVM.
Build verification environments including stimulus, checkers, assertions, and coverage trackers.
Execute verification plans for design bring-up and regression enabling.
Debug test failures and fix bugs identified during regression cycles.
Track and report verification progress using bugs and coverage metrics.
Utilize LLMs and related technologies to improve verification efficiency and quality.
Perform verification for RTL freeze and tape-out sign-off.

What we're looking for

BS degree in a technical subject area.
Minimum 10 years of relevant industry experience.
Deep knowledge of OOP, SystemVerilog, and UVM (preferred).
Deep knowledge in developing scalable and portable test-benches (preferred).
Strong experience with verification methodologies and tools such as simulators, waveform viewers, and coverage collection (preferred).
Working experience using LLMs for efficiency and quality (preferred).
Experience with power-aware (UPF) or similar verification methodology (preferred).
Excellent knowledge of scripting languages such as Python, Perl, or TCL (preferred).

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