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About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
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As a Design Verification Engineer, you will join the hardware team to ensure bug-free first silicon for SoC and IP designs. You will be responsible for all phases of pre-silicon verification, including establishing methodologies, developing test plans based on micro-architecture, and building scalable, portable verification environments. Your daily work involves creating stimulus, checkers, assertions, and trackers while executing design bring-up and regression testing to close bugs before tape-out. You will utilize SystemVerilog, UVM, and scripting languages like Python, Perl, or TCL to stress designs. Additionally, you will leverage LLMs and related technologies to improve execution efficiency and quality. The role involves solving complex hardware problems through coverage tracking, gate level simulations, and potentially utilizing power-aware methodologies, formal verification, or emulation techniques to ensure high-quality silicon for various integrated circuits.
What does a Design Verification Engineer earn?
Median $177300 from 31 postings across 8 companies.
Develop detailed test and coverage plans based on the micro-architecture of SoC/IP designs.
Establish scalable and portable verification methodologies suitable for specific IP requirements.
Build verification environments including stimulus, checkers, assertions, trackers, and coverage components.
Execute design bring-up and regression testing to identify and fix hardware bugs.
Track and report verification progress using metrics such as bug counts and coverage percentages.
Utilize LLMs and related technologies to improve execution efficiency and verification quality.
Perform pre-silicon verification activities including RTL freeze and tape-out sign-off.
What we're looking for
BS degree in a technical subject area.
Minimum 10 years of relevant industry experience.
Deep knowledge of OOP, SystemVerilog, and UVM (preferred).
Deep knowledge in developing scalable and portable test-benches (preferred).
Strong experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, and gate level simulations (preferred).
Working experience using LLMs for efficiency and quality (preferred).
Experience with power-aware (UPF) or similar verification methodology (preferred).
Excellent knowledge of scripting languages such as Python, Perl, or TCL (preferred).