Design Verification Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Beaverton, OR
Posted
17 days ago
Freshness
Confirmed live yesterday

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Salary context

How this pay compares to similar roles

Similar $199k
$141k most similar roles pay here $240k

This listing doesn't post a salary. Most similar roles pay $168,500–$229,100.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

As a Design Verification Engineer within the Hardware Technology organization, you will be responsible for verifying the functionality and performance of premier SOCs. You will work at the heart of the chip design effort by collaborating with design, micro-architecture, and software teams to ensure quality across various subsystems or IPs. Your daily responsibilities include reviewing architecture specifications, developing test plans, creating coverage plans, and defining next-generation verification methodologies and testbenches. The role involves addressing complex technical challenges such as neural engine hardware, memory controllers, high-speed IO standards like PCI Express, and cryptographic algorithms. To succeed, you must possess skills in SystemVerilog, UVM, and digital simulation, along with proficiency in Python or Perl for scripting. You will apply knowledge of computer architecture and data structures to validate critical components including power management, networking protocols, and display subsystems.

What does a Design Verification Engineer earn?

Median $195800 from 78 postings across 10 companies.

See salary data

What you'll do

  • Verify the functionality and performance of premier System-on-Chip (SOC) designs, IPs, or subsystems.
  • Review design and architecture specifications to ensure technical requirements are met.
  • Develop comprehensive test plans, coverage plans, and verification methodologies for next-generation products.
  • Build and maintain complex testbenches using SystemVerilog and UVM methodologies.
  • Define and execute test cases based on specific functional goals and corner conditions.
  • Analyze hardware components including memory controllers, security modules, and high-speed I/O standards.
  • Use Python or Perl scripting to automate verification tasks and improve workflows.
  • Communicate with design, architecture, and software teams to define use cases for testing.

What we're looking for

  • Minimum of BS degree and 10 years of relevant industry experience.
  • Skilled in digital verification including constrained random, functional coverage, code coverage, and assertion methodology (preferred).
  • Knowledge of SystemVerilog, digital simulation, and debug (preferred).
  • Knowledge of computer architecture and digital design fundamentals (preferred).
  • Good software programming skills with knowledge of data structures and algorithms (preferred).
  • Experience with Python, Perl, or similar scripting languages (preferred).
  • Knowledge of verification methodologies like UVM (preferred).
  • Experience with C/C++ and assembly is a plus (preferred).

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