CAD Engineer - Design Verification Methodology

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: Beaverton, OR
Posted: 124 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $188k

$129k most similar roles pay here $236k

This listing doesn't post a salary. Most similar roles pay $162,375–$214,000.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · CAD Engineer - Design Verification Methodology

Role Posting Log in to save

As a CAD Engineer – Design Verification Methodology, you will join the Silicon Technologies group to develop, maintain, and enhance sophisticated software systems used for regression-testing silicon designs in software simulation. Your primary responsibility involves identifying and reporting defects in chip designs to ensure successful tape-outs of high-performance, power-efficient processors and system-on-chip architectures. You will collaborate with EDA vendors to integrate new capabilities into commercial tools while providing technical guidance to engineers across the extended CAD team. The role requires proficiency in Python, with additional experience in TCL, Perl, C, or C++. You will work within a domain focused on design verification methodology using tools such as VCS, Xcelium, Modelsim, Verdi, and Indago. Knowledge of Verilog, SystemVerilog, VHDL, and emulation tools from Cadence or Synopsys is also relevant to this technical role.

Skills

Python TCL Perl Verilog SystemVerilog VHDL VCS Xcelium Modelsim Cadence Synopsys Verdi Indago C C++ Machine Learning RTL

What you'll do

Develop, maintain, and enhance sophisticated software systems for regression-testing silicon designs.
Identify and report defects in chip designs during the software simulation phase.
Diagnose root causes of complex technical problems within the CAD team.
Collaborate with EDA vendors to integrate new capabilities into commercial tools and resolve issues.
Implement new functionality to solve emerging problems or optimize existing methodologies.
Provide technical guidance and support to engineers facing design verification challenges.

What we're looking for

Bachelor's degree and at least 10 years of relevant experience are required.
Experience developing, maintaining, and enhancing existing systems for regressing RTL is required.
Proficiency in Python programming is required.
Experience debugging vendor tool problems is required.
Knowledge of Verilog and SystemVerilog is preferred; familiarity with VHDL is a plus.
Experience with VCS, Xcelium, or Modelsim simulation tools is preferred.
Experience with Cadence or Synopsys Emulation tools is preferred.
Proficiency in TCL, Perl, C, or C++ is preferred.

Save