CAD Engineer, Design Verification Methodology

What you'll do

• Develop, maintain, and enhance software systems for regression-testing silicon designs in software simulation.
• Identify and report defects in chip designs to ensure successful silicon tape-outs.
• Diagnose the root cause of complex technical problems and provide guidance to other engineers.
• Work with EDA vendors to incorporate new tool capabilities and resolve technical issues.
• Implement new functionality to solve emerging problems or optimize existing regression methods.
• Use Python to build and maintain sophisticated CAD software systems.
• Support Design Verification and chip design engineering efforts through CAD tool development.

What we're looking for

• Minimum of a BS degree plus 10 years of relevant experience.
• Experience developing, maintaining, and enhancing an existing system for regressing RTL.
• Experience debugging vendor tool problems.
• Python programming background is required.
• Experience with TCL or Perl (preferred).
• Experience with artificial intelligence and machine learning (preferred).
• Experience interacting with DV teams to solve problems (preferred).
• Experience implementing new functionality to solve emerging problems or optimize existing methods (preferred).
• MSEE/CE/CS degree (preferred).
• Knowledge in Verilog and SystemVerilog; familiarity with VHDL (preferred).
• Experience with VCS, XCelium, or Modelsim simulation tools (preferred).
• Experience with Cadence or Synopsys Emulation tools (preferred).
• Good communication skills are required; prior customer support experience is a plus (preferred).
• Familiarity with Verdi and/or Indago (preferred).
• Knowledge of C and C++ (preferred).