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RTL Verilog SystemVerilog Python Perl SoC CDC Synthesis VCS GDB Debussy dc_shell DFT Microarchitecture Scripting Silicon Debug Physical Design +12 more Show less

Verilog system Verilog UVM Python C++ Perl C Shell MySQL PHP Linux Unix Windows HDL Simulation Debugging Oscilloscopes Logic Analyzers +13 more Show less

PCB Design Cadence Allegro Mentor Expedition SPICE PCIe Gen5/6 LPDDR4x/5x DDR4/5 Ethernet JTAG Signal Integrity Power Integrity BMC x86 ARM SMBus PMBus SPI PWM Oscilloscopes Logic Analyzers Circuit Simulation +16 more Show less

Schematic Capture Circuit Design FPGA CPLD Board Bring-up Signal Integrity Verilog VHDL Python Perl Tcl Spectrum Analyzers Protocol Analyzers Digital Logic +9 more Show less

Schematic Capture Circuit Design FPGA CPLD Board Bring-up Signal Integrity High-Speed Interface Design Verilog VHDL Python Perl Tcl Spectrum Analyzers Signal Generators eLoads Protocol Analyzers +11 more Show less

PCB Design Cadence Allegro Mentor Expedition SPICE PCIe Gen5/6 LPDDR4x/5x DDR4/5 Ethernet Signal Integrity Power Integrity JTAG BMC SMBus PMBus SPI PWM x86 ARM Oscilloscopes Logic Analyzers Circuit Simulation +16 more Show less

PCB Design Cadence Allegro Mentor Expedition Signal Integrity Power Integrity PCIe Gen5/6 LPDDR4x/5x DDR4/5 Ethernet JTAG SPICE x86 ARM BMC SMBus PMBus SPI PWM Oscilloscopes Logic Analyzers Circuit Simulation +16 more Show less

x86 SoC Signal Integrity Power Delivery Network DDR4/5 LPDDR4/5 Ethernet Linux Windows Server C C++ Python Perl Oscilloscope JBERT Circuit Design root-cause analysis +12 more Show less