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IC Package Design Flip-chip BGA ASIC SerDes Signal Integrity Power Integrity HBM DDR5 Cadence APD Allegro Package Designer Cadence SKILL Physical Design Layout RF Microwave ADC DAC +12 more Show less

RTL Design Verilog Python Logic Synthesis DFT Physical Design Timing Closure Silicon Debug Power Optimization OCV Effects SOC Verification +6 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Logic Equivalence Checking MTBF Analysis Timing Closure DFT Python Perl TCL Make EDA Tools ECO Generation +8 more Show less

RTL NoC SoC Synthesis STA CDC Lint Cache Coherency MESI MOESI Directory-based Coherence Memory Hierarchy Crossbars Arbitration Scripting Front-end Synthesis +11 more Show less

Physical Design Python C++ Perl DFT Place and Route Timing Closure Power/Clock/Reset Distribution Agentic AI Chiplet Packaging Algorithm Development +7 more Show less

Verilog System Verilog ASIC SoC RTL Design Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization +11 more Show less

RTL-to-GDSII Physical Design Static Timing Analysis STA Innovus Tempus Primetime Redhawk Voltus Calibre Python TCL Perl Clock Tree Synthesis CTS Power Integrity Floorplanning Place and Route Equivalence Checks +14 more Show less

RTL Design Verilog SystemVerilog Python Perl SoC Architecture CDC Synthesis VCS dc_shell GDB Debussy DFT Physical Design Object-Oriented Programming Performance Analysis Design Automation +12 more Show less

RTL Design Verilog Python Logic Synthesis DFT Physical Design Timing Closure Silicon Debug Power Optimization OCV SOC Verification +6 more Show less

Verilog Python Perl Unix Linux Makefiles ASIC Verification RTL Generation CDC Synthesis DevOps Digital Design Hardware Design IP Development +9 more Show less

Verilog System Verilog RTL Design ASIC SoC Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization +11 more Show less

RTL Design Verilog System Verilog ASIC SoC Python AXI AHB Synthesis Timing Closure HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems +10 more Show less

Verilog System Verilog RTL Design ASIC SoC Synthesis Timing Closure AXI AHB Python HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems Formality Check Silicon Bring-up +12 more Show less

SystemVerilog UVM ASIC Verification Python C/C++ Perl VCS Verdi DFT UPF Machine Learning SoC Functional Coverage Assertion-based Verification GDS +10 more Show less

RTL NoC ASIC Design Synthesis STA CDC Lint Cache Coherency MESI MOESI Memory Hierarchy Crossbars Arbitration Front-end Synthesis +9 more Show less

RTL NoC Crossbars Cache Coherency MESI MOESI Directory-based Coherence Synthesis STA CDC Lint Memory Hierarchy SoC Front-end Synthesis +9 more Show less

Verilog SystemVerilog RTL Design Synopsys Synthesis Python C++ C Computer Architecture Low Power Design Coverage-based Design Verification OpenGL Vulkan Direct3D ASIC GPU DSP Machine-Learning +12 more Show less

ASIC SystemVerilog Verilog UVM Python Perl VCS Verdi Xcelium RTL Pre-silicon Verification infrastructure, automation Simulation Debug Root-cause Analysis +10 more Show less

ASIC Physical Design Logic Equivalence Checking Formal Verification Logic Synthesis Clock Domain Crossing MTBF Analysis ECO Generation Python Perl TCL Make Synopsys Cadence Hardware Architecture Timing Closure +10 more Show less

Digital Design ASIC FPGA Emulation Silicon Bring-up Mixed Signal Design MIPI HDMI TCON Micro-architecture Verification Emulation Validation Characterization Debug +9 more Show less