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Verilog Python Perl Unix Linux Makefiles ASIC Verification RTL Generation DevOps Synthesis CDC Digital Design Hardware Design +8 more Show less

RTL Verilog Python ASIC DFT Logic Synthesis PPA Silicon Debug Timing Closure Power Optimization Cross-talk OCV Scripting +8 more Show less

RTL Verilog SystemVerilog Python Perl SoC CDC Synthesis VCS GDB Debussy dc_shell DFT Microarchitecture Scripting Silicon Debug Physical Design +12 more Show less

ASIC UVM SystemVerilog Verilog Python Perl VCS Verdi Xcelium Automation RTL Pre-silicon Verification Scripting Infrastructure Simulation Debug Metrics +12 more Show less

ASIC Physical Design Logic Synthesis Formal Verification Equivalence Checking RTL Timing Closure Clock Domain Crossing MTBF Analysis Synopsys Cadence Python TCL Perl Make EDA Tools Netlisting ECO Generation +12 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Equivalence Checking DFT Python TCL Perl Make EDA Tools Netlist Quality Check Timing Closure ECO Generation Hardware Architecture +9 more Show less

Digital Design FPGA Silicon Bring-up Characterization Mixed Signal Design MIPI HDMI TCON Micro-architecture Emulation Verification Validation +7 more Show less

ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design +8 more Show less

ASIC Design RTL Verilog Micro-architecture Logic Synthesis Timing Analysis VLSI Python LLM Agentic AI RAG Vector Databases Machine Learning Computer Architecture Digital Systems Data Structures Algorithms +12 more Show less

UVM SystemVerilog Verilog SystemC Matlab C DPI-C Formal Verification RTL ASIC Digital Verification Scripting CMOS +8 more Show less

ASIC Floorplan Physical Design SOC CPU GPU DFT Place and Route Timing Closure Python C++ Perl Agentic AI Algorithm Development Chiplet Power/Clock/Reset Distribution +11 more Show less

System Verilog UVM SystemC Verilog C++ Formal Verification ASIC Design RTL Linux Windows OOP Simulation Functional Coverage Digital Design Computer Architecture +10 more Show less

ASIC SOC Physical Design RTL2GDSII Static Timing Analysis STA Floorplanning Place and Route DFT Scan MBIST LBIST FinFET CMOS Python TCL Perl Bash Makefile EDA Tools +15 more Show less

ASIC Floorplan VLSI Computer Architecture Verilog System Verilog Python Perl C/C++ CAD Physical Design Timing Closure Clock Distribution Packaging +8 more Show less

ASIC VLSI RTL to GDSII Synthesis Place and Route STA Timing Closure PPA DFT Hspice Finesim Spectre RedHawk SeaHawk Voltus Python Perl TCL C/C++ +14 more Show less