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Python Perl Verilog SystemVerilog dc_shell VCS Debussy GDB Kubernetes Terraform CI/CD Git Unix/Linux CDC multiple-power-domains performance-analysis data-flow object-oriented-programming +13 more Show less

Python Perl Verilog SystemVerilog dc_shell VCS Debussy GDB Kubernetes Terraform CI/CD Git Unix/Linux +8 more Show less

Verilog Python Perl Unix/Linux Makefiles CI/CD +1 more Show less

Verilog Python RTL Logic Synthesis CI/CD Sub-micron Silicon Issues Clocking Networks Clocks Controller Power Optimization Noise Analysis Cross-talk OCV Effects Scalable Designs Silicon Debug +9 more Show less

RTL2GDSII EDA tools CMOS digital design principles Standard cells DFT Scan MBIST LBIST Physical design flows +4 more Show less

Python CI/CD

Verilog Python RTL Docker CI/CD VLSI Sub-micron silicon issues Noise Cross-talk OCV effects Clocking networks Power Optimization Physical Implementation DFx Timing Closure +10 more Show less

Verilog SystemVerilog Python Perl C++ CAD VLSI ComputerArchitecture ChipFloorplan PowerClockDistribution Packaging P&R TimingClosure +8 more Show less

Perl TCL Make Python Synopsys Cadence Logic Synthesis Equivalence Checking Formal Verification Clock Domain Crossing Checks MTBF Analysis RTL Design EDA Tools AI Utilization +9 more Show less

Python Shell Synthesis Place_and_Route TCL Perl Makefile CI/CD VLSI SoC Power_Optimization Performance_Optimization Area_Optimization Cost_Optimization Rapid_Prototyping +10 more Show less

Python Verilog RTL design SOC architecture CI/CD Docker Git Unix/Linux VCS Perl TCL Makefiles SVN Mentor Graphics Calibre Cadence Genus Synthesis Suite Synopsys IC Compiler II +11 more Show less

SystemVerilog UVM C++ Verilog Linux Windows Python Git CI/CD Jenkins Docker Kubernetes AWS Google Cloud Platform PostgreSQL Mentor Graphics Calibre Cadence Incisive Simulator Formal Verification Random Testing Directed Testing +15 more Show less

SystemVerilog UVM Python Verilog VCS Verdi OOPS CI/CD +3 more Show less