Cellular ASIC Design Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Austin, TX
Posted: 57 days ago
Nearby: 99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $194k

$143k most similar roles pay here $235k

This listing doesn't post a salary. Most similar roles pay $165,200–$223,700.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Cellular ASIC Design Engineer

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The Technical Lead role within the Hardware team requires an experienced professional to oversee Power, Performance, Area, and Cost optimizations for System-on-Chip (SoC) designs. This individual will lead the development and scripting of methodologies and test chip block implementations, driving rapid prototyping efforts. The ideal candidate should possess a strong background in physical design challenges, with proficiency in synthesis, place-and-route tools, and implementation exploration. They will work on large-scale projects that demand meticulous attention to detail and innovative solutions to complex technical problems, contributing significantly to the advancement of cutting-edge SoC technology.

Skills

Python Shell Synthesis Place_and_Route TCL Perl Makefile CI/CD VLSI SoC Power_Optimization Performance_Optimization Area_Optimization Cost_Optimization Rapid_Prototyping

What you'll do

Lead power, performance, area, and cost optimization efforts for System-on-Chips (SoCs).
Develop and implement rapid prototyping methodologies for test chip block creation.
Script efficient workflows to enhance design validation processes.
Provide technical guidance on synthesis, place and route tool usage.
Explore implementation strategies to address physical design challenges.

What we're looking for

Experience in optimizing Power, Performance, Area, and Cost for SoCs.
Expertise in rapid prototyping and scripting methodologies.
Proficiency in test chip block implementation.
Strong understanding of physical design challenges.
Skillful use of synthesis, place and route tools.
Ability to explore and implement design solutions.

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