Cellular ASIC Design Engineer

Apple Inc

Confirmed live 2 days ago Trusted

Quick summary

Work type: On-site
Location: Austin, TX
Posted: 149 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $196k

$141k most similar roles pay here $240k

This listing doesn't post a salary. Most similar roles pay $168,000–$223,650.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Cellular ASIC Design Engineer

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As a Cellular ASIC Design Engineer within the Hardware Technologies group, you will design and optimize high-performance, power-efficient cellular chips and system-on-chips using advanced process technologies like 3nm and 2nm. You will develop methodologies for area efficiency, power optimization, and design technology co-optimization while establishing standards for synthesis, place-and-route, timing closure, and signoff processes. Your daily work involves building automation tools, performing Spice simulations, conducting power analysis, and implementing voltage scaling techniques like clock gating and dynamic frequency scaling. You will utilize a technical stack including DC, ICC2, PT, RedHawk, and Hspice, while applying programming skills in Python, Perl, TCL, Unix shell, and C/C++. Additionally, you will leverage machine learning modeling for predictive analysis to solve complex scaling bottlenecks and improve design metrics across the RTL to GDS digital flow.

Skills

ASIC VLSI RTL to GDSII Synthesis Place and Route STA Timing Closure PPA DFT Hspice Finesim Spectre RedHawk SeaHawk Voltus Python Perl TCL C/C++

What you'll do

Develop and optimize design methodologies for synthesis, place-and-route, timing closure, and signoff processes.
Create scripts and automation tools using Python, Perl, or TCL to improve design productivity.
Perform power optimization techniques including clock gating, power gating, and dynamic voltage scaling.
Conduct Spice simulations and STA correlation to validate performance across various PVT corners.
Analyze design databases and silicon validation data to identify bottlenecks in advanced technology nodes.
Execute Design Technology Co-optimization (DTCO) to improve PPA metrics for 3nm and 2nm processes.
Drive DFT methodology improvements including scan insertion, ATPG, and built-in self-test strategies.
Apply machine learning models to analyze design databases and post-silicon data for predictive optimization.

What we're looking for

Minimum of a Bachelor's degree and 10 years of relevant industry experience.
VLSI background with hands-on experience in RTL to GDSII flows.
Experience optimizing Power, Performance, Area, and Cost (PPA) for SoCs.
Expertise in SoC power flows and Vmin optimization.
Experience in Design Technology Co-optimization and solving scaling bottlenecks in new technology nodes.
Proficiency in rapid prototyping and scripting of methodologies and test chip block implementation.
Strong programming skills in Python, Perl, TCL, Unix shell, or C/C++.
Ability to apply data science and ML analytics for frontend, backend, and post-silicon data analysis.

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