ASIC Design Verification Engineer in Austin, Texas | Advanced Micro Devices, Inc

Amd

Quick summary

Work type: On-site
Location: Austin, TX
Salary: $200,000–$200,000 / yr
Posted: 94 days ago
Closes: Mar 9, 2027
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $188k

This role $200k

$146k most similar roles pay here $228k

This role pays more than 61% of similar roles. Most pay $161,200–$214,862 — the shaded band above. At the midpoint, this role pays about $200k versus about $188k for comparable roles.

Based on 240 similar postings.

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About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 71 open roles on FindRole.

Listed pay typically runs $178,400–$178,400 across 71 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer in Austin, Texas | Advanced Micro Devices, Inc

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The AMD UMC Team is seeking a senior ASIC Design Verification Engineer to join its dynamic and innovative group focused on developing cutting-edge DDR/LPDDR technologies for data centers and machine learning applications. In this role, you will collaborate with IP architects to design verification architectures and develop comprehensive test plans while taking ownership of key features across multiple projects. Your day-to-day responsibilities include creating and maintaining VIPs, libraries, and verification environments using System Verilog/UVM/SystemC, as well as triaging regressions and analyzing functional coverage. You will also deploy industry-leading methodologies like UVM and formal verification to ensure high-quality IP delivery. Ideal candidates possess strong analytical skills, proficiency in digital design and computer architecture, and experience with tools such as Verilog, C/C++, and Linux/Windows environments.

Skills

SystemVerilog UVM C++ Verilog Linux Windows Python Git CI/CD Jenkins Docker Kubernetes AWS Google Cloud Platform PostgreSQL Mentor Graphics Calibre Cadence Incisive Simulator Formal Verification Random Testing Directed Testing

What you'll do

Develop and maintain VIP, libraries, and verification environments using System Verilog/UVM.
Create test plans and develop random/directed testcases for complex IP blocks.
Analyze functional coverage and debug regressions in simulation environments.
Deploy industry-leading verification methodologies like UVM and formal verification.
Reproduce post-silicon functional bugs in dynamic simulations or formal verification.

What we're looking for

Extensive ASIC design and verification experience required.
Proficient in System Verilog/UVM for test plan development and regression testing.
Strong analytical skills with keen attention to detail and problem-solving abilities.
Experience in developing, modifying, and maintaining VIPs and verification environments.
Knowledge of digital design, computer architecture, and security verification preferred.
BS/MS degree in Engineering (Electrical/Electronics/Computer) or Computer Science.

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Santa Clara, CA +3 97 days ago $121,680–$121,680

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