ASIC Design Verification Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$116,000–$189,750 / yr
Employment
Full-time
Posted
2 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $187k
This role $153k
$103k $238k
below market most similar roles pay here above market

This role pays less than 77% of similar roles. Most pay $157,837–$216,250 — the blue band above. At the midpoint, this role pays about $153k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1668 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 657 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · ASIC Design Verification Engineer

Role Posting Log in to save

The ASIC Design Verification Engineer - New College Grad 2026 joins the System-On-Chip group to work on system-level IP responsible for measuring performance across multiple projects. The primary focus involves verifying and improving verification methodologies for the corresponding RTL design. Key responsibilities include designing and maintaining unit level and sub-system verification environments, developing test plans, and creating UVM components, sequences, tests, and scoreboards. The role requires launching regressions, resolving issues, and automating manual steps for builds and triages. Candidates must possess skills in SystemVerilog, UVM, and OOPS based programming, along with Python scripting. Required technical knowledge includes RTL design in Verilog, computer architecture fundamentals, and familiarity with verification tools like VCS and debug tools like Verdi to ensure high quality functional coverage.

Skills

System Verilog UVM Python Verilog RTL VCS Verdi OOPS Computer Architecture ASIC Verification Sub-system Verification Functional Coverage Scripting

What you'll do

  • Design and maintain unit-level and sub-system verification environments.
  • Develop and execute test plans based on architecture specifications.
  • Create UVM components, sequences, tests, and scoreboards.
  • Sign off on verification efforts using high-quality code and functional coverage.
  • Launch regressions, resolve issues, and meet DV milestone targets.
  • Automate manual steps for builds, regressions, and triages.
  • Improve testbench efficiency by implementing the latest verification techniques.

What we're looking for

  • Complete an MS or higher in Computer or Electrical Engineering (or equivalent experience).
  • Experience in System Verilog, UVM, and general OOPS based programming.
  • Strong coding skills in Python or other industry-standard scripting languages.
  • Strong understanding of RTL design using Verilog.
  • Good understanding of computer architecture fundamentals.
  • Familiarity with verification tools such as VCS or equivalent simulation tools.
  • Familiarity with debug tools like Verdi.

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