ASIC Design Verification Engineer - New College Grad 2026

Nvidia

Quick summary

Work type: On-site
Location: Austin, TX
Salary: $116,000–$189,750 / yr
Posted: 148 days ago

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $186k

This role $153k

$104k most similar roles pay here $231k

This role pays less than 78% of similar roles. Most pay $156,412–$216,250 — the shaded band above. At the midpoint, this role pays about $153k versus about $186k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer - New College Grad 2026

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NVIDIA's SOC group seeks an entry-level ASIC Verification Engineer to join its team, focusing on verifying system-level IP responsible for performance measurement across multiple projects. This role involves designing and maintaining unit level/sub-system verification environments, developing test plans based on architecture specifications, creating UVM components, sequences, tests, and scoreboards, and ensuring high-quality code with robust functional coverage. The ideal candidate will automate manual steps in build and regression processes, collaborate closely with architects, designers, and software engineers to meet project goals, and continuously improve verification methodologies using the latest techniques. Essential skills include a strong background in System Verilog, UVM, Python scripting, RTL design (Verilog), computer architecture fundamentals, and familiarity with verification tools like VCS and debug tools such as Verdi.

Skills

SystemVerilog UVM Python Verilog VCS Verdi OOPS CI/CD

What you'll do

Design and maintain unit level/sub-system verification environment.
Develop and execute test plans based on architecture specifications.
Create UVM components, sequences, tests, and scoreboards.
Ensure high-quality code and functional coverage in verification efforts.
Automate manual steps for build, regression, and issue resolution processes.
Collaborate with cross-functional teams to achieve project goals efficiently.

What we're looking for

MS or higher in Computer/Electrical Engineering or equivalent experience.
Proficiency in System Verilog and UVM verification methodologies.
Strong coding skills in Python or other scripting languages.
Solid understanding of RTL design (Verilog) and computer architecture.
Experience designing and maintaining unit/sub-system verification environments.
Familiarity with verification tools like VCS and debug tools like Verdi.

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