Apple Inc

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About Apple Inc

Published by FindRole · most recent listing · Methodology

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3542 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2744 roles with salary data.

Most-posted roles

How Apple Inc posts

Employer behavior measured from this employer’s own listings, including ones that have since closed.

77.5%
of open roles publish a salary range

Layoffs · WARN filings

Trending down

1,074 workers affected across 15 filings since 2023.

Source: U.S. Worker Adjustment and Retraining Notification (WARN) Act filings, via WARN Feed (CC BY 4.0).

Open roles

3,542 total

SoC UPF Methodology Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live yesterday Low trust
UPF Power Intent Python Tcl AI/ML CMOS Power Design Static Verification Dynamic Verification RTL-to-GDSII VSILP VCLP CLP place-and-route
10+ yrs exp
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SoC Power Flow Methodology Engineer

San Diego, CA 45 days ago $142,300–$263,300
Actively hiring Confirmed live yesterday High trust Competitive pay
VLSI SoC Design Python Perl TCL AI machine learning RTL Synthesis place-and-route Power Analysis Flow Development Algorithm Design Software Testing
3+ yrs exp
Save

SoC Power Flow Methodology Engineer

Cupertino, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live 2 days ago High trust Competitive pay
VLSI SoC Design Python Perl TCL AI machine learning RTL Synthesis place-and-route Power Analysis Flow Development Algorithm Design Software Testing
3+ yrs exp
Save

SoC Power Flow Methodology Engineer

Beaverton, OR 45 days ago
Actively hiring Confirmed live yesterday High trust
VLSI SoC Design Python Perl TCL AI machine learning RTL Synthesis place-and-route Power Analysis Software Testing Flow Development Algorithm Design
3+ yrs exp
Save

SoC Power Flow Methodology Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live yesterday High trust
VLSI SoC Design Python Perl TCL AI machine learning RTL Synthesis place-and-route Power Analysis Flow Development Algorithm Design Software Testing
3+ yrs exp
Save

SoC Power Validation Engineer

San Diego, CA 45 days ago $175,000–$308,500
Actively hiring Confirmed live 2 days ago High trust Above market
SoC Power Validation C Assembly CMOS Oscilloscope Multi-meter Low-power Digital Design Simulation tool chains
10+ yrs exp
Save

SoC Power Validation Engineer

Cupertino, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday High trust Above market
SoC Power Validation ASIC C Assembly CMOS Oscilloscope Multi-meter Low-power Digital Design Simulation tool chains
10+ yrs exp
Save

SoC Power Validation Engineer

San Diego, CA 45 days ago $142,300–$263,300
Actively hiring Confirmed live yesterday High trust Competitive pay
SoC Power Validation C Assembly CMOS Oscilloscope multi-meter Low-power Digital Design
3+ yrs exp
Save

SoC Power Validation Engineer

Cupertino, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live 2 days ago High trust Competitive pay
SoC Power Validation C Assembly CMOS Oscilloscope Multi-meter Low-power Digital Design tool chains
3+ yrs exp
Save

SoC DFT Engineer

Cupertino, CA 45 days ago $123,700–$186,900
Actively hiring Confirmed live yesterday Low trust Below market
DFT ATPG JTAG MBIST Verilog VHDL STA SDF Design Verification Silicon Debug ATE Waveform Debugging Scripting
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SoC DFT Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live yesterday Low trust
DFT ATPG JTAG MBIST Verilog VHDL STA SDF Design Verification Silicon Debug ATE Waveform Debugging Simulators Scripting
Save

SoC DFT DV Engineer

Cupertino, CA 45 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Low trust Below market
DFT SoC Python Perl TCL Gate Level Simulation Random Verification Coverage Analysis Assertions Logic Design Test Benches Automation Scripts Regressions
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SoC DFT DV Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live 2 days ago Low trust
DFT SoC Gate Level Simulation Python Perl TCL Random Verification Coverage Analysis Assertions Verification Plans Test Benches Automation Scripts Logic Design
Save

SoC DFT Engineer

Cupertino, CA 45 days ago $123,700–$186,900
Actively hiring Confirmed live yesterday Low trust Below market
DFT ATPG JTAG MBIST Verilog VHDL STA SDF Design Verification Silicon Debug ATE Waveform Debugging Scripting
Save

SoC DFT Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live 2 days ago Low trust
DFT ATPG JTAG MBIST Verilog VHDL STA SDF Design Verification Silicon Debug ATE Waveform Debugging Simulators Scripting
Save

SoC Full Chip DV Engineer

Cupertino, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Low trust Above market
SystemVerilog Verilog UVM Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Python Perl C++ Assembly Digital Simulation Computer Architecture Digital Design Debug
10+ yrs exp
Save

SoC Full Chip DV Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live 2 days ago Low trust
SystemVerilog Verilog UVM Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Python Perl C++ Assembly Digital Simulation Computer Architecture Digital Design Scripting
10+ yrs exp
Save

SoC Full Chip DV Engineer

Cupertino, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live 2 days ago Low trust Competitive pay
SystemVerilog Verilog UVM Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Python Perl C++ Assembly Digital Simulation Computer Architecture Digital Design Scripting
3+ yrs exp
Save

SoC Full Chip DV Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live 2 days ago Low trust
SystemVerilog Verilog UVM Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Python Perl C++ Assembly Digital Simulation Computer Architecture Digital Design Scripting
3+ yrs exp
Save

SoC Full Chip DV Engineer

Cupertino, CA 45 days ago $129,300–$194,700
Actively hiring Confirmed live 2 days ago Low trust Below market
SystemVerilog Verilog UVM Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Python Perl C++ Assembly Digital Simulation Computer Architecture Digital Design Scripting
Save