SoC DFT Engineer

What you'll do

• Develop and implement DFT architecture and infrastructure for SoC designs.
• Verify DFT implementations and execute ECOs in coordination with the DV team.
• Generate structural test vectors and analyze results to improve coverage.
• Resolve STA, physical, power, and logical issues in collaboration with designers.
• Coordinate with test engineers to bring up test vectors on silicon.
• Debug Compressed ATPG patterns, MBIST, and JTAG/1500 related issues.
• Develop STA constraints for DFT modes and perform SDF simulations.
• Analyze ATE data using scripting to support efficient silicon debug experiments.

What we're looking for

• Bachelor of Science degree required.
• Knowledge of industrial standards and practices in DFT, including ATPG, JTAG, MBIST, and trade-offs between test quality and time (preferred).
• Experience developing DFT specifications and driving DFT architecture and methods for designs (preferred).
• Knowledge of Verilog and/or VHDL, along with experience using simulators and waveform debugging tools (preferred).
• Knowledge of industry standards for DFT and design tools (preferred).
• Proven understanding of design verification methodologies for validating DFT implementation in simulation pre-silicon (preferred).
• Experience debugging Compressed ATPG patterns, MBIST, and JTAG/1500 related issues (preferred).
• Experience with STA constraints development and analysis for DFT modes and SDF simulations (preferred).