Wireless SOC Verification Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Irvine, CA
Salary: $175,000–$308,500 / yr
Posted: 17 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $242k

$124k most similar roles pay here $328k

This role pays more than 85% of similar roles. Most pay $168,500–$241,750 — the shaded band above. At the midpoint, this role pays about $242k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · Wireless SOC Verification Engineer

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As a Wireless SOC Verification Engineer within the Wireless SOC team, you will perform pre-silicon RTL verification of block and top-level systems to ensure tape-out readiness. You will be responsible for creating coverage-driven verification plans from specifications, architecting highly reusable UVM testbenches, and integrating complex multi-instance VIPs and sub-system test suites. Your daily work involves verifying high-speed layered protocols, power management designs using UPF simulations, and various peripherals including PCIe, memory controllers, and USB. You will collaborate with cross-functional teams to resolve issues involving firmware-hardware interactions and multi-chip debug architectures. The role requires expertise in SystemVerilog and UVM methodology to validate complex wireless protocol chip requirements. You will navigate technical challenges involving low-power schemes, bus fabrics, and NOC architectures to ensure the reliability of sophisticated wireless systems.

Skills

SystemVerilog UVM ASIC SOC PCIe UPF Formal Verification RTL DMA DDR USB AHB AXI NoC Power Management coverage driven verification Bluetooth

What you'll do

Create coverage-driven verification plans from specifications and refine them to meet target goals.
Architect highly reusable UVM-based testbenches and integrate complex multi-instance VIPs into the SOC level.
Perform pre-silicon RTL verification for both individual blocks and top-level SOC designs.
Execute power management verification using low-power methodologies and UPF simulations for various power scenarios.
Develop and implement directed test cases to ensure coverage of high-speed layered protocols and wireless requirements.
Verify hardware-firmware interactions and complex multi-chip SOC debug architectures.
Collaborate with cross-functional teams to integrate and verify overall SOC designs before tape-out.
Work with methodology architects to improve verification metrics and internal processes.

What we're looking for

Bachelor of Science degree and at least 10 years of relevant industry experience.
Proven track record of working a full ASIC cycle from concept to tape-out and bring-up.
Expertise in SystemVerilog coding and UVM methodology.
Experience taping out large SOC systems with embedded processor cores (preferred).
Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, and AXI based bus architecture in a UVM environment (preferred).
Experience with Formal Verification (preferred).
In-depth knowledge of low power design, UPF integration, boot-up, power-cycling, and HW/FW interaction verification (preferred).
Excellent communication and problem-solving skills (preferred).

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