Wireless SOC Verification Engineer

Apple Inc

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $184,700–$324,800 / yr
Posted: 17 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $255k

$121k most similar roles pay here $347k

This role pays more than 98% of similar roles. Most pay $168,500–$241,750 — the shaded band above. At the midpoint, this role pays about $255k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · Wireless SOC Verification Engineer

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As a Wireless SOC Verification Engineer, you will join the Wireless SOC team to verify complex systems at the heart of mobile networking. You will perform pre-silicon RTL verification for both blocks and top-level SOCs while collaborating with cross-functional teams to ensure tape-out readiness. Your daily responsibilities include creating coverage-driven verification plans from specifications, architecting highly reusable UVM testbenches, and integrating multi-instance VIPs and sub-system test suites. You will work on high-speed layered protocols, power management designs using UPF simulations, and complex hardware-firmware interactions. The role requires expertise in SystemVerilog and the UVM methodology to validate components like PCIe, memory controllers, and bus architectures. This position addresses the technical challenges of multi-chip SOC debug architecture, low-power design schemes, and ensuring robust performance for wireless protocol chip requirements within a large-scale silicon design environment.

Skills

SystemVerilog UVM ASIC SOC PCIe UPF Formal Verification RTL DMA DDR USB AHB AXI NoC Power Management low power design Coverage Driven Verification

What you'll do

Create coverage-driven verification plans from technical specifications to meet defined coverage targets.
Architect highly reusable UVM-based testbenches and integrate complex multi-instance VIPs into the SOC level.
Perform pre-silicon RTL verification for both individual blocks and top-level SOC designs.
Execute power management verifications using low-power methodologies and UPF simulations for power up/down scenarios.
Develop and implement directed test cases to verify high-speed layered protocols and wireless requirements.
Integrate and verify complex subsystems including PCIe, memory controllers, and multi-processor systems.
Collaborate with architecture and firmware teams to resolve hardware/firmware interaction issues.
Improve verification metrics and methodologies in coordination with DV methodology architects.

What we're looking for

Bachelor of Science degree and at least 10 years of relevant industry experience.
Proven track record of working a full ASIC cycle from concept to tape-out and bring-up.
Expertise in SystemVerilog coding and UVM methodology.
Experience taping out large SOC systems with embedded processor cores (preferred).
Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, and AXI based bus architectures in a UVM environment (preferred).
Experience with Formal Verification (preferred).
In-depth knowledge and experience with low power design, UPF integration, and HW/FW interaction verification (preferred).
Excellent communication and problem-solving skills (preferred).

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