Wireless Design Verification Engineer

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Irvine, CA
Salary
$175,000–$308,500 / yr
Posted
14 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k
This role $242k
$131k most similar roles pay here $327k

This role pays more than 82% of similar roles. Most pay $168,500–$241,750 — the shaded band above. At the midpoint, this role pays about $242k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2925 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2305 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Wireless Design Verification Engineer

As a Senior Wireless Design Verification Engineer, you will join the Wireless Connectivity team to ensure first-time-right silicon success for state-of-the-art WiFi SoCs. You will lead subsystem-level verification from test planning and environment definition through feature closure, focusing on controllers, datapaths, protocols, and low power capabilities. Your daily work involves architecting sophisticated UVM testbench environments, developing constrained random scenarios for complex multi-domain behaviors, and driving coverage-driven methodologies. To succeed, you must possess deep expertise in SystemVerilog, UVM, and ASIC verification flows, along with proficiency in Python scripting for automation and metric analysis. You will also utilize transaction-level modeling, DPI integration, and bus functional models to verify advanced wireless features. This role addresses the technical challenges of developing multi-gigabit wireless technology and ensuring robust integration across a complex product ecosystem.

What you'll do

  • Lead subsystem-level verification from initial test planning and environment definition through final feature closure.
  • Architect sophisticated UVM testbench environments, infrastructure frameworks, and reusable verification IP with automation capabilities.
  • Develop constrained random scenarios for complex protocols and multi-domain behaviors.
  • Drive coverage-driven methodologies and metric analysis frameworks to ensure silicon success.
  • Create verification strategies for wireless features across the product ecosystem.
  • Debug complex issues and drive technical decisions through cross-functional collaboration.
  • Develop Python scripts for automation, metric analysis, and infrastructure development.

What we're looking for

  • Bachelor of Science degree and at least 10 years of relevant industry experience.
  • Demonstrated expertise verifying complex digital ASICs with a track record of successful silicon tapeouts.
  • Deep knowledge of ASIC verification flows using SystemVerilog and UVM, including testbench architecture and coverage-driven methodologies.
  • Experience developing verification environments from scratch and bringing up complex designs in simulation.
  • Experience with constrained random testing, functional coverage, and assertion-based verification.
  • Exposure to ASIC architectures including datapath operation, hardware acceleration, and low-power mechanisms (preferred).
  • Experience with system-models, DPI integration, BFMs, transaction-level modeling, and verification IP development (preferred).
  • Proficiency in Python scripting for automation, metric analysis, and infrastructure development (preferred).

More like this

Similar roles

Wireless Design Verification Engineer

Apple Inc

San Diego, CA 14 days ago $175,000–$308,500
SystemVerilog UVM ASIC Verification Python Functional Coverage Assertion-Based Verification DPI Bus Functional Models Transaction-Level Modeling Formal Verification Low-Power Methodologies Regression Infrastructure Verification IP SOC / integration
10+ yrs exp

Wireless Design Verification Engineer

Apple Inc

Sunnyvale, CA 14 days ago $184,700–$324,800
SystemVerilog UVM ASIC Verification Python Functional Coverage Assertion-Based Verification DPI Bus Functional Models Transaction-Level Modeling Formal Verification Low-Power Methodologies Regression Infrastructure Verification IP SOC / integration
10+ yrs exp

Wireless PHY Design Verification Engineer

Apple Inc

San Diego, CA 12 days ago $175,000–$308,500
UVM SystemVerilog ASIC Verification IEEE 802.11 DSP Assertion-Based Verification Functional Coverage Bus Functional Models Scoreboarding Transaction-Level Modeling
10+ yrs exp

Wireless PHY Design Verification Engineer

Apple Inc

Sunnyvale, CA 12 days ago $184,700–$324,800
UVM SystemVerilog ASIC Verification IEEE 802.11 DSP Assertion-Based Verification Functional Coverage Bus Functional Models Scoreboarding Transaction-Level Modeling
10+ yrs exp

Wireless PHY Design Verification Engineer

Apple Inc

Sunnyvale, CA 164 days ago $129,300–$225,300
UVM SystemVerilog ASIC Verification IEEE 802.11 DSP Assertion-Based Verification Functional Coverage Bus Functional Models Scoreboarding Transaction-Level Modeling Bluetooth Cellular

Wireless PHY Design Verification Engineer

Apple Inc

San Diego, CA 164 days ago $122,700–$214,300
UVM SystemVerilog ASIC Verification IEEE 802.11 DSP Assertion-Based Verification Functional Coverage Scoreboarding Bus Functional Models Wireless Protocols Bluetooth Cellular Transaction-Level Modeling