Wireless Design Verification Engineer

What you'll do

• Lead subsystem-level verification from initial test planning and environment definition through feature closure.
• Architect sophisticated UVM testbench environments, infrastructure frameworks, and reusable verification IP with automation.
• Develop constrained random scenarios for complex protocols and multi-domain behaviors.
• Drive coverage-driven methodologies and metric analysis frameworks to ensure silicon success.
• Create verification strategies for wireless features across the product ecosystem.
• Perform design bring-up in simulation for complex digital ASICs.
• Develop Python scripts for automation, metric analysis, and infrastructure development.
• Integrate system models, DPI, and bus functional models into the verification flow.

What we're looking for

• Bachelor of Science degree and at least 10 years of relevant industry experience.
• Demonstrated expertise verifying complex digital ASICs with a track record of successful silicon tapeouts.
• Deep knowledge of ASIC verification flows using SystemVerilog and UVM, including testbench architecture and coverage-driven methodologies.
• Experience developing verification environments from scratch and bringing up complex designs in simulation.
• Experience with constrained random testing, functional coverage, and assertion-based verification.
• Exposure to ASIC architectures including datapath operation, hardware acceleration, and low-power mechanisms (preferred).
• Experience with system-models, DPI integration, BFMs, transaction-level modeling, and verification IP development (preferred).
• Proficiency in Python scripting for automation, metric analysis, and infrastructure development (preferred).