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Senior Staff Design Verification Engineer

Amd

San Jose, CA 53 days ago $200,000–$300,000
Actively hiring Confirmed live today High trust Above market
Verilog SystemVerilog UVM DFT RTL Design Python Tcl Perl Shell Static Timing Analysis ASIC SoC FPGA Synopsys Cadence PCIe SerDes HBM Synthesis Place-and-Route
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