Senior Design Verification Engineer

Amd

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $141,760–$212,640 / yr
Posted: 2 days ago
Freshness: Confirmed live today
Closes: Oct 27, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $201k

This role $177k

$131k $244k

below market most similar roles pay here above market

This role pays less than 72% of similar roles. Most pay $169,625–$233,312 — the blue band above. At the midpoint, this role pays about $177k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 500 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 500 roles with salary data.

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At a glance

TL;DR · Senior Design Verification Engineer

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The SR Design Verification Engineer joins the Network Technologies Solutions Group to drive verification closure on complex, high-performance ASIC designs for next-generation networking products. You will develop robust UVM-based testbench architectures, create test plans, and build SystemVerilog components including stimulus generators, agents, scoreboards, and assertions for IP, subsystem, and SoC levels. Daily responsibilities include executing verification plans, triaging regressions, and root-causing failures across RTL, interfaces, and system interactions. You will utilize tools such as VCS, Verdi, and coverage analysis suites while employing Python, Tcl, and Make for automation. Key technical requirements include expertise in SystemVerilog, UVM, and protocols like PCIe, DDR, and Ethernet. You will collaborate with RTL design and architecture teams to ensure high-quality deliverables for high-performance data-path components.

What does a Design Verification Engineer earn in California?

Median $195350 from 60 postings across 7 companies.

See salary data

Skills

SystemVerilog UVM VCS Verdi DVE Python Tcl Perl Shell PCIe Ethernet DDR AXI DMA FPGA HAPS UPF C/C++ Make Formal Verification

What you'll do

Develop UVM-based testbench architectures for IP, subsystem, and SoC-level verification.
Create test plans, feature mappings, and coverage strategies for complex networking and data-path IP.
Develop SystemVerilog components including stimulus generators, agents, scoreboards, checkers, and assertions.
Execute verification plans, triage regressions, and debug architectural, functional, and performance issues.
Root-cause complex failures across RTL, testbenches, and interfaces like PCIe, DDR, and Ethernet.
Optimize simulation performance, coverage closure, and verification sign-off methodologies.
Improve verification infrastructure and automation using Python, Tcl, or Make scripts.
Provide technical leadership and mentorship to junior verification engineers.

What we're looking for

Bachelor’s Degree in Electrical/Computer Engineering or related field.
Master’s Degree (preferred).
Expert-level knowledge of SystemVerilog and UVM.
Strong hands-on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE).
Proven experience verifying complex IP/subsystems using test plans, coverage, and constrained-random methodologies.
Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data-path components.
Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure.
Experience with performance verification, power-aware verification (UPF), or formal verification (preferred).

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