Design Verification Engineer

Amd

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $166,400–$249,600 / yr
Posted: 101 days ago
Freshness: Confirmed live yesterday
Closes: Jun 2, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $188k

This role $208k

$122k most similar roles pay here $263k

This role pays more than 69% of similar roles. Most pay $159,750–$216,250 — the shaded band above. At the midpoint, this role pays about $208k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Design Verification Engineer

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As a Design Verification Engineer within the Network Technologies Solutions Group, you will drive verification closure on complex, high-performance ASIC designs for advanced data center networking products. You will develop robust UVM-based testbench architectures at the IP, subsystem, and SoC levels while creating test plans and coverage strategies for networking and data-path components. Your daily work involves developing SystemVerilog components like scoreboards and assertions, performing regression triage, and root-causing failures across RTL, PCIe, DDR, and Ethernet interfaces. You will utilize industry-standard tools including VCS and Verdi, while utilizing Python, Tcl, or Shell for automation. The role requires expertise in constrained-random methodologies and performance verification to solve complex architectural issues within high-performance networking pipelines. You will collaborate with cross-functional teams to ensure high-quality deliverables across the distributed services platform.

Skills

SystemVerilog UVM VCS Verdi DVE Python Tcl Perl Shell PCIe Ethernet DDR AXI DMA UPF Formal Verification C/C++ Make HAPS FPGA

What you'll do

Develop robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification.
Create comprehensive test plans, feature mapping, and coverage strategies for complex networking data-path IPs.
Build high-quality SystemVerilog components including stimulus generators, scoreboards, checkers, and functional coverage models.
Execute verification plans while performing regression triage and debugging architectural, functional, and performance issues.
Root-cause complex failures across RTL, testbench, and hardware interfaces like PCIe, DDR, and Ethernet.
Optimize simulation performance, coverage closure, and overall verification sign-off methodologies.
Develop automation scripts and infrastructure enhancements using Python, Tcl, or Shell.
Provide technical leadership and mentorship to junior engineers within the verification team.

What we're looking for

Bachelor's Degree in Electrical/Computer Engineering or a related field; Master's degree preferred.
Expert-level knowledge of SystemVerilog and UVM.
Experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE).
Proven experience verifying complex IP/subsystems using test plans, coverage, and constrained-random methodologies.
Strong debugging skills across architecture, RTL, and testbench layers.
Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, or DMA engines.
Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure.
Preferred experience in performance verification, power-aware verification (UPF), formal verification, or FPGA/HAPS flows.