Design Verification Engineer

Amd

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $166,400–$249,600 / yr
Posted: 147 days ago
Freshness: Confirmed live today
Closes: Jun 2, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k

This role $208k

$138k $262k

below market most similar roles pay here above market

This role pays more than 59% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $208k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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JOB TITLE: Design Verification Engineer The Design Verification Engineer joins the Network Technologies Solutions Group to support the development of high-performance DPU and software stack products for data center networking. You will drive verification closure on complex, high-performance ASIC designs by developing robust UVM-based testbench architectures for IP, subsystem, and SoC levels. Daily responsibilities include creating test plans, developing SystemVerilog components like stimulus generators and scoreboards, and performing regression triage to root-cause failures across RTL and interfaces such as PCIe, DDR, and Ethernet. You will utilize industry-standard tools including VCS, Verdi, and coverage tools, while using Python, Tcl, and Make for automation. The role requires expertise in constrained-random methodologies to ensure the functional and performance integrity of high-speed networking and data-path components.

What does a Design Verification Engineer earn in California?

Median $199500 from 57 postings across 7 companies.

See salary data

Skills

SystemVerilog UVM VCS Verdi DVE Python Tcl Perl Shell PCIe Ethernet DDR AXI DMA FPGA HAPS UPF C/C++ Make Formal Verification

What you'll do

Develop UVM-based testbench architectures for IP, subsystem, and SoC-level verification.
Create test plans, feature mappings, and coverage strategies for complex networking and data-path IP.
Develop SystemVerilog components including stimulus generators, agents, scoreboards, checkers, and assertions.
Execute verification plans, triage regressions, and debug architectural, functional, and performance issues.
Root-cause complex failures across RTL, testbench, and interfaces like PCIe, DDR, and Ethernet.
Optimize simulation performance, coverage closure, and verification sign-off methodologies.
Build automation and infrastructure enhancements using Python, Tcl, or Make.
Provide technical leadership and mentor junior verification engineers.

What we're looking for

Bachelor’s Degree in Electrical/Computer Engineering or related field.
Master’s Degree (preferred).
Expert-level knowledge of SystemVerilog and UVM.
Strong hands-on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE).
Proven experience verifying complex IP/subsystems using test plans, coverage, and constrained-random methodologies.
Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data-path components.
Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure.
Experience with performance verification, power-aware verification (UPF), or formal verification (preferred).

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