ASIC Design Engineer
Qualcomm
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How this pay compares to similar roles
This role pays less than 66% of similar roles. Most pay $167,175–$222,000 — the shaded band above. At the midpoint, this role pays about $175k versus about $195k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 621 open roles on FindRole.
Listed pay typically runs $147,900–$222,500 across 601 roles with salary data.
Most-posted roles
At a glance
SoC Power Design Engineer (Engineer - Staff Eng) joins the Global SoC Power team to implement and validate low power design intent requirements at the SoC level. This role involves collaborating with frontend RTL, DFT, Synthesis, Design Verification, and Physical Design teams to ensure power requirements are met from pre-silicon to post-silicon stages. Key responsibilities include generating and validating UPF designs, reviewing IP power budgets, performing power analysis for clocktrees and peak power, and creating power models for chipset teams. The candidate will utilize hardware description languages like Verilog, VHDL, and System Verilog, alongside scripting in Perl, Tcl, or Python. Technical expertise is required in power-aware implementation flows including UPF/CPF/Conformal Low Power Check, as well as tools such as PtPx, PowerArtist, Prime Power, and PowerPro to manage multi-voltage domain designs and power gating.
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