SoC Power Design Engineer

Qualcomm

Confirmed live 2 days ago Trusted

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$140,000–$210,000 / yr
Posted
17 days ago
Freshness
Confirmed live 2 days ago
Closes
Feb 22, 2027

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $195k
This role $175k
$129k most similar roles pay here $246k

This role pays less than 66% of similar roles. Most pay $167,175–$222,000 — the shaded band above. At the midpoint, this role pays about $175k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 621 open roles on FindRole.

Listed pay typically runs $147,900–$222,500 across 601 roles with salary data.

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At a glance

TL;DR · SoC Power Design Engineer

SoC Power Design Engineer (Engineer - Staff Eng) joins the Global SoC Power team to implement and validate low power design intent requirements at the SoC level. This role involves collaborating with frontend RTL, DFT, Synthesis, Design Verification, and Physical Design teams to ensure power requirements are met from pre-silicon to post-silicon stages. Key responsibilities include generating and validating UPF designs, reviewing IP power budgets, performing power analysis for clocktrees and peak power, and creating power models for chipset teams. The candidate will utilize hardware description languages like Verilog, VHDL, and System Verilog, alongside scripting in Perl, Tcl, or Python. Technical expertise is required in power-aware implementation flows including UPF/CPF/Conformal Low Power Check, as well as tools such as PtPx, PowerArtist, Prime Power, and PowerPro to manage multi-voltage domain designs and power gating.

What you'll do

  • Generate and validate power intent designs (UPF) at the SoC level.
  • Review IP designs to ensure they meet low power implementation requirements and budget targets.
  • Execute power-aware implementation flows including UPF/CPF and Conformal Low Power Checks.
  • Perform power analysis and projections for SoC baseline power using industry-standard tools.
  • Develop and deliver SoC power models and dashboards to the chipset teams.
  • Track IP power development through all design milestones to ensure leakage and dynamic power targets are met.
  • Collaborate with CAD and vendors to improve power modeling, clock power analysis, and flow tools.

What we're looking for

  • Bachelor's degree in Science, Engineering, or related field with 4+ years of ASIC design, verification, validation, or integration experience.
  • Master's degree in Science, Engineering, or related field with 3+ years of ASIC design, verification, validation, or integration experience.
  • PhD in Science, Engineering, or related field with 2+ years of ASIC design, verification, validation, or integration experience.
  • Proficiency in ASIC frontend development, logic design, RTL coding, verification, synthesis, and timing closure.
  • Proficiency in hardware description languages including Verilog, VHDL, and System Verilog.
  • Experience with power-aware implementation flows, including UPF/CPF/Conformal Low Power Check.
  • Proficiency in scripting using Perl, Tcl, or Python.
  • Master's degree in Electrical or Computer Engineering (preferred).

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