SoC Physical Design Engineer, Power Delivery

Apple Inc

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: Waltham, MA
Salary: $165,800–$292,400 / yr
Posted: 104 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $203k

This role $229k

$133k $309k

below market most similar roles pay here above market

This role pays more than 76% of similar roles. Most pay $177,250–$229,100 — the blue band above. At the midpoint, this role pays about $229k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · SoC Physical Design Engineer, Power Delivery

Role Posting Log in to save

The SoC Physical Design Engineer - Power Delivery works within a team responsible for completing partition place and route from netlist to tapeout, including automation tasks for Apple SOC. The role involves developing features and methodology solutions for a wide range of SOC partitions while ensuring a strong and DRC-clean power grid. Key responsibilities include collaborating multi-functionally with CAD, Physical Verification, Electrical analysis, and PnR teams. The candidate must utilize technical expertise in automation for Physical Design and block execution. Required skills include programming in TCL and Python to write maintainable and reusable scripts. The position requires knowledge of ASIC integration, floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration using industry standard tools for PNR, Voltage Drop Analysis, STA, and Layout Verification.

Skills

Physical Design ASIC Integration TCL Python Place and Route Floorplanning Power Distribution STA Layout Verification Voltage Drop Analysis DRC Hard IP Integration CAD Electrical Analysis

What you'll do

Complete partition place and route from netlist to tapeout for Apple SoCs.
Develop automation tasks for physical design using TCL and Python.
Design and maintain a DRC-clean power grid for various SoC partitions.
Create features and methodology solutions for wide-scale SoC partition use.
Perform voltage drop analysis and layout verification using industry-standard tools.
Manage floorplanning, clock distribution, and hard IP integration for ASIC designs.
Execute block-level physical design tasks and automation scripts.

What we're looking for

Minimum BS degree and 10+ years of relevant industry experience.
Familiarity with ASIC integration, including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration.
Experience with scripting and programming to write maintainable and reusable scripts of medium complexity in TCL and/or Python.
Understanding of industry standard tools for PNR, Voltage Drop Analysis, STA, and Layout Verification.
Experience with automation for Physical Design, including block execution (preferred).
Experience with cross-functional collaboration with CAD, Physical Verification, Electrical analysis, and PnR teams to ensure electrically robust power grids (preferred).
Experience with latest technology nodes tapeout (preferred).