Pre-Silicon Validation Engineer

Qualcomm

Confirmed live 2 days ago Trusted

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$98,500–$147,700 / yr
Posted
15 days ago
Freshness
Confirmed live 2 days ago
Closes
Feb 23, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $190k
This role $123k
$83k most similar roles pay here $240k

This role pays less than 93% of similar roles. Most pay $163,000–$216,062 — the shaded band above. At the midpoint, this role pays about $123k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Pre-Silicon Validation Engineer

#Pre-Silicon Validation Engineer The #Pre-Silicon Validation Engineer joins the ASICS Engineering team to support the development and validation of complex ASIC and FPGA-based designs. This role involves developing, deploying, and maintaining emulation environments for SoC designs while porting RTL designs onto platforms like Cadence Palladium, Siemens Veloce, or FPGA prototyping systems. The engineer will build testbenches, transactors, and verification infrastructure to enable early hardware and software co-validation. Day-to-day responsibilities include analyzing functional and performance issues, creating Python automation scripts for regression execution, and performing waveform analysis for root-cause identification. Key technical requirements include proficiency in SystemVerilog, C/C++, Linux shell scripting, and Python. The role addresses the critical challenge of hardware/software co-validation within complex SoC architectures, utilizing AI-driven productivity tools to accelerate verification, debug efficiency, and overall engineering workflows across various high-speed interfaces.

What you'll do

  • Develop, deploy, and maintain ASIC and FPGA emulation environments for complex SoC designs.
  • Port RTL designs onto industry-standard platforms such as Cadence Palladium or Siemens Veloce.
  • Build testbenches, transactors, and verification infrastructure using SystemVerilog and C/C++.
  • Analyze and debug functional, performance, and system-level issues within emulation environments.
  • Create Python scripts and workflows to automate regression execution and improve debugging efficiency.
  • Develop methodologies for waveform analysis, signal tracing, and root-cause identification of failures.
  • Apply AI-assisted tools and techniques to accelerate verification and engineering productivity.

What we're looking for

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 0 to 2+ years of experience in ASIC verification, FPGA prototyping, or hardware emulation.
  • Proficiency in SystemVerilog and C/C++ for developing testbenches and verification infrastructure.
  • Expertise in Python programming and Linux environments including shell scripting.
  • Experience with ASIC and FPGA emulation platforms such as Cadence Palladium, Siemens Veloce, or Synopsys ZeBu.
  • Knowledge of SoC architectures, bus protocols, and hardware/software co-validation.
  • Skills in RTL debugging, waveform analysis, and design verification methodologies.
  • Ability to use AI-powered engineering tools and automation scripts to improve productivity.

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