This role pays less than
81%
of similar roles. Most pay
$159,937–$216,250
— the shaded band above.
At the midpoint, this role pays about
$152k
versus about
$188k
for comparable roles.
Based on 240 similar postings.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
598 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 586 roles with salary data.
The Design Verification Engineer joins the Verification & Validation team within the Compute Silicon & Manufacturing Engineering organization to support cloud hardware infrastructure. In this role, you will own or lead the verification of components used in Fabric Interconnect by collaborating with partner teams to define strategies and test plans. You will develop UVM-based or Formal verification environments, run and debug simulations, and apply random-stimulus and coverage-based techniques to identify bugs. The position involves innovating verification efficiency through new methodologies, tools, and generative AI solutions while mentoring others in your areas of expertise. Key technical requirements include experience with SystemVerilog Test Bench, Python for post-processing, and protocols such as CHI, AMBA, PCIe, or CXL. You will solve complex hardware challenges related to coherency, virtualization, and security within the cloud infrastructure domain.
Own or lead the verification of components used in Fabric Interconnect.
Define verification strategies and test plans by collaborating with partner teams.
Develop UVM-based or Formal verification environments to run and debug simulations.
Apply random-stimulus and coverage-based techniques to identify bugs and meet goals.
Innovate new methodologies and tools to improve overall verification efficiency.
Integrate generative AI solutions into daily verification workflows.
Coach and mentor team members in specific areas of technical expertise.
What we're looking for
A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 2+ years of technical engineering experience.
A Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 1+ year of technical engineering experience.
Ability to pass the Microsoft Cloud Background Check every two years.
Ability to provide proof of citizenship or protected status to access export-controlled information.
Experience with UVM-based or Formal verification environments, including running and debugging simulations.
Experience in pre-silicon subsystem or IP verification.
Knowledge of CHI and AMBA protocols, as well as fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, or protocol bridges.
Proficiency in SystemVerilog, Python for scripting/post-processing, and applying generative AI to daily tasks.
UVM
System Verilog
Python
C++
System C
SVA
Coverage Driven Verification
LLM
Prompt Engineering
RTL Simulation
4G/5G
3GPP
AXI
AHB
NoC
Bus Fabric
Perl
Automation
UVM
System Verilog
Python
C++
System C
SVA
coverage driven verification
Constraint Random Testing
LLM
Prompt Engineering
RTL Simulation
4G
5G
3GPP
AXI
AHB
NoC
Bus Fabric
Automation