Design Verification Engineer

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $122,700–$214,300 / yr
Posted: 148 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $188k

This role $168k

$111k most similar roles pay here $232k

This role pays less than 67% of similar roles. Most pay $159,750–$216,250 — the shaded band above. At the midpoint, this role pays about $168k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

Role Posting Log in to save

As a Design Verification Engineer, you will join the silicon design group to ensure the quality and reliability of next-generation cellular systems, specifically focusing on high-throughput cellular baseband modems and transceiver link controllers for SoCs. You will construct detailed test plans, create coverage-driven verification plans from specifications, and architect reusable UVM-based test benches featuring components like stimulus, checkers, VIPs, and reference models. Your daily work involves implementing test plans from RTL simulation bring-up to sign-off while managing regressions and reporting progress against coverage metrics. You will utilize SystemVerilog, UVM, SystemC, C/C++, Python, Perl, and SVA. Additionally, you will leverage Large Language Models and MCPs to enhance verification workflows. The role addresses complex technical challenges in cellular protocols, advanced fabric protocols, and low-power architectures to ensure tape-out readiness for high-performance communication systems.

Skills

UVM System Verilog Python C++ C SVA coverage driven verification LLM Prompt Engineering RTL Simulation 4G/5G 3GPP AXI AHB NoC Bus Fabric Automation

What you'll do

Construct detailed test plans including use cases and coverage goals from design specifications.
Architect reusable UVM-based test benches featuring stimulus, checkers, VIPs, and reference models.
Develop coverage-driven and directed test cases to validate complex IP and subsystem designs.
Implement test plans from RTL simulation bring-up through final sign-off while debugging failures.
Integrate Large Language Models (LLMs) and ML-driven workflows to improve verification efficiency.
Maintain regression suites and report progress against coverage metrics and test plans.
Develop Python-based automation solutions to enhance the overall verification process.

What we're looking for

Must have a bachelor's degree or higher.
Knowledge of System Verilog and UVM is required.
Experience with System C, C/C++, Python, and Perl is required.
Ability to develop and establish Design Verification (DV) methodologies.
Ability to use Large Language Models (LLMs) and Model Context Protocols (MCPs).
Ability to develop Python-based automation solutions.
Understanding of constraint random testing, SystemVerilog Assertions (SVA), and coverage-driven verification.
Experience with 4G/5G cellular physical layer operation, bus architectures (AXI, AHB), and embedded processor cores is preferred.

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