SOC Verification and Methodology Engineer

Qualcomm

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$174,400–$261,600 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k
This role $218k
$131k $276k
below market most similar roles pay here above market

This role pays more than 70% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $218k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · SOC Verification and Methodology Engineer

Role Posting Log in to save

The SOC Verification and Methodology Engineer joins the Global SOC organization to ensure the quality and functionality of premium tier smartphone System-on-Chip designs. Working within the ASIC Engineering group, you will develop verification methodologies, create detailed test plans, and execute verification tests to identify and resolve complex design issues. Your daily work involves implementing SystemVerilog and UVM based verification skills, including assertion and coverage-based methodologies. You will verify varied design IPs and system-level integration aspects for products spanning low power Snapdragon chips, Machine Learning, and Autonomous driving. Key technical requirements include experience with CPU architecture, AMBA Bus, DDR, and GPU. You will also utilize scripting languages like Perl or Python and potentially work with Formal tools to push the frontiers of hardware verification.

Skills

ASIC Design Verification SystemVerilog UVM SOC Architecture CPU Architecture ARM AMBA Bus DDR GPU Python Perl UCIe CXL Pre-silicon Emulation Coverage-based Verification Tapeout

What you'll do

  • Develop detailed verification plans and infrastructure based on design specifications.
  • Implement and execute verification test cases to identify and resolve complex design issues.
  • Analyze SystemVerilog assertions and code, toggle, and functional coverage.
  • Validate varied design IPs and system-level integration aspects.
  • Develop innovative verification methodologies and tools to improve test bench efficiency.
  • Maintain quality standards and best practices throughout the test and verification processes.
  • Manage verification workflows from initial test planning through to tapeout.

What we're looking for

  • Bachelor's degree in Science, Engineering, or related field with 6+ years of ASIC design, verification, validation, or integration experience.
  • Master's degree in Science, Engineering, or related field with 5+ years of ASIC design, verification, validation, or integration experience.
  • PhD in Science, Engineering, or related field with 4+ years of ASIC design, verification, validation, or integration experience.
  • Minimum 10+ years of design verification experience.
  • Good understanding of SystemVerilog/UVM based verification skills and experience with assertion and coverage-based verification methodology.
  • Experience handling verification from test planning to tapeout for large-size hardware designs.
  • Master's degree in Science, Engineering, or related field (preferred).
  • 15+ years of industry experience with SOC architecture, CPU architecture, DSP, AMBA Bus, DDR, GPU, and Multimedia (preferred).

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