SOC Verification and Methodology Engineer

Qualcomm

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$164,000–$246,000 / yr
Posted
73 days ago
Freshness
Confirmed live yesterday
Closes
Dec 27, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k
This role $205k
$127k most similar roles pay here $259k

This role pays more than 67% of similar roles. Most pay $168,500–$216,250 — the shaded band above. At the midpoint, this role pays about $205k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · SOC Verification and Methodology Engineer

As a SOC Verification and Methodology Engineer within the Global SOC organization, you will ensure the quality and functionality of System-on-Chip designs through comprehensive verification processes. You will be responsible for developing verification plans based on design specifications, creating test infrastructure, and executing test cases to identify and resolve complex issues. Your daily work involves implementing and analyzing SystemVerilog assertions and coverage while collaborating with architects, designers, and silicon teams. The role requires expertise in SystemVerilog, UVM-based methodologies, and assertion-based verification for large-scale hardware designs from planning through tapeout. You will utilize advanced tools to verify varied design IPs and system-level integration. The work focuses on the technical challenges of 5G product lines, including low power Snapdragon chips, Machine Learning applications, and autonomous driving systems involving complex SoC architectures.

What you'll do

  • Develop detailed verification plans based on design specifications and define the scope of verification infrastructure.
  • Implement and execute verification test cases to identify and resolve complex design issues.
  • Analyze SystemVerilog assertions and manage code, toggle, and functional coverage metrics.
  • Create and implement advanced verification methodologies to improve the quality and efficiency of test benches.
  • Verify diverse design IPs and perform system-level integration validation for SoC designs.
  • Develop innovative solutions to technical verification challenges with minimal guidance.
  • Manage the full verification lifecycle from initial test planning through to tapeout for large-scale hardware designs.

What we're looking for

  • Bachelor's degree in Science, Engineering, or a related field.
  • Minimum 10 years of design verification experience for senior positions.
  • At least 6 years of experience with a Bachelor's, 5 years with a Master's, or 4 years with a PhD.
  • Proficiency in SystemVerilog and UVM based verification methodologies.
  • Experience with assertion and coverage-based verification methods.
  • Experience managing the full verification lifecycle from test planning to tapeout for large hardware designs.
  • Knowledge of SoC architecture, CPU architecture (ARM), DSP, AMBA Bus, DDR, GPU, and Multimedia.
  • Proficiency in scripting languages such as Perl or Python is preferred.

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