Design Verification Engineer

Amd

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$136,000–$204,000 / yr
Posted
89 days ago
Freshness
Confirmed live today
Closes
Jul 29, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k
This role $170k
$125k $241k
below market most similar roles pay here above market

This role pays less than 75% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $170k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Design Verification Engineer

The Design Verification Engineer will join a leading team to drive the delivery of high-quality, industry-leading technologies and differentiating IPs. Working alongside RTL, firmware, circuit, and architecture experts, the engineer will develop and maintain tests for functional verification, including building directed and random verification tests. Daily responsibilities involve debugging test failures to determine root causes, resolving design defects, and managing functional and code coverage verification. The role requires proficiency in Verilog, SystemVerilog, and UVM, along with experience in C/C++. Candidates should possess skills in scripting languages like Python, Perl, and TCL to support ASIC design verification. The work focuses on complex processor architecture, specifically addressing technical challenges within DDR, Memory Controllers, and PHY verification to ensure robust performance for next-generation hardware.

What does a Design Verification Engineer earn in California?

Median $199500 from 57 postings across 7 companies.

See salary data

What you'll do

  • Develop and maintain tests for functional verification.
  • Build directed and random verification tests for complex processor architectures.
  • Debug test failures to identify root causes and resolve design defects.
  • Work with RTL and firmware engineers to correct test issues and design bugs.
  • Perform functional and code coverage verification.
  • Provide technical support to other engineering teams.
  • Debug RTL code using industry-standard simulation tools.

What we're looking for

  • Bachelor's, Master's, or Ph.D. degree in Computer Engineering or Electrical Engineering.
  • Experience with Verilog, SystemVerilog, and modern verification libraries like UVM (preferred).
  • Experience with C/C++ (preferred).
  • Strong ASIC design verification experience (preferred).
  • Experience or background with DDR or Memory Controller (preferred).
  • Experience with scripting languages like Python, Perl, and TCL (preferred).
  • Experience with PHY Verification (preferred).
  • Proficient in debugging RTL code using simulation tools (preferred).

More like this

Similar roles

Design Verification Engineer

Amd

Santa Clara, CA 147 days ago $166,400–$249,600
SystemVerilog UVM VCS Verdi DVE Python Tcl Perl Shell PCIe Ethernet DDR AXI DMA FPGA HAPS UPF C/C++ Make Formal Verification

Design Verification Engineer

Apple Inc

Beaverton, OR 40 days ago
SystemVerilog UVM Digital Simulation Python Perl C/C++ Assembly Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Computer Architecture Digital Design Data Structures Algorithms PCI Express DisplayPort MIPI
10+ yrs exp

Design Verification Engineer

Apple Inc

Beaverton, OR 40 days ago
SystemVerilog Verilog Python Perl C++ C Assembly Digital Design Computer Architecture Digital Simulation Debug

Design Verification Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
SystemVerilog UVM Python Perl C++ Assembly Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Digital Simulation Computer Architecture PCI Express DisplayPort MIPI Ethernet TCP/IP NVLink Infiniband Data Structures and Algorithms
10+ yrs exp

Design Verification Engineer

Apple Inc

Cupertino, CA 54 days ago $155,896–$225,300
System Verilog UVM C C++ Python Perl EDA Tools Digital Design Computer Architecture Constrained Random Verification Functional Coverage ASIC Design Flow High-speed Interface Protocols Regression Analysis Verification IP
3+ yrs exp

Design Verification Engineer

Apple Inc

Austin, TX 137 days ago
UVM System Verilog Python C++ System C Perl Coverage Driven Verification SVA LLM ML 4G 5G 3GPP AXI AHB NOC Bus Fabric RTL Simulation