Design Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $181,100–$318,400 / yr
Posted: 57 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $184k

This role $250k

$114k most similar roles pay here $340k

This role pays more than 93% of similar roles. Most pay $158,762–$209,750 — the shaded band above. At the midpoint, this role pays about $250k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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As a Design Verification Engineer at the senior level within our silicon design group, you will play a pivotal role in verifying innovative high-throughput cellular baseband modems and RF link controllers for Apple's SOCs. Your daily tasks include crafting comprehensive UVM verification environments, developing coverage-driven test cases, and collaborating with multi-functional teams to ensure tape-out readiness. You will leverage Large Language Models (LLMs) and machine learning techniques to enhance verification processes, improve efficiency, and maintain regressions while reporting progress against coverage metrics. The ideal candidate possesses strong knowledge of System Verilog and UVM, proficiency in Python and scripting languages like Perl, and experience with constraint random testing and SVA. Additionally, familiarity with 4G/5G cellular physical layer operation (3GPP) and verification of embedded processor cores is preferred, offering opportunities to deepen expertise in complex IP architectures and advanced fabric protocols.

Skills

SystemVerilog UVM Python Perl LLMs MCPs C C++ SVA Coverage-driven verification RTL simulation Constraint random testing AHB AXI NOC Bus Fabric Large Language Models Prompt engineering

What you'll do

Construct detailed test plans for design components through collaboration with multi-functional teams.
Create coverage-driven verification plans from specifications, refining them to meet coverage targets.
Architect UVM-based, reusable test benches including stimulus, checkers, VIPs and reference models.
Leverage Large Language Models (LLMs) to enhance verification processes, improving efficiency and quality.
Design ML-driven workflows to increase team productivity and overall verification quality.
Implement test plans from RTL simulation bring-up to sign-off; report and debug failures.

What we're looking for

Strong knowledge of System Verilog and Universal Verification Methodology (UVM).
Proficient in developing detailed test plans and coverage-driven verification strategies.
Skilled in creating reusable UVM-based test benches with VIPs and reference models.
Experience using Large Language Models to enhance verification processes.
Hands-on experience with constraint random testing, SVA, and Python automation scripts.
Expertise in verifying complex IP and subsystem designs for high-throughput systems.
Strong problem-solving skills and ability to work collaboratively across multi-functional teams.

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