Design Verification Engineer

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $184,700–$324,800 / yr
Posted: 148 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $188k

This role $255k

$113k most similar roles pay here $347k

This role pays more than 96% of similar roles. Most pay $159,750–$216,062 — the shaded band above. At the midpoint, this role pays about $255k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

Role Posting Log in to save

As a Design Verification Engineer, you will join the silicon design group to ensure the quality and reliability of next-generation cellular systems. You will be responsible for constructing detailed test plans, creating coverage-driven verification plans from specifications, and architecting reusable UVM-based test benches featuring components like stimulus, checkers, VIPs, and reference models. Your daily work involves implementing test plans from RTL simulation bring-up to sign-off while managing regressions and reporting progress against coverage metrics. You will utilize SystemVerilog, UVM, SystemC, C/C++, Python, Perl, SVA, and LLM-driven workflows to enhance verification efficiency. The role focuses on the technical challenges of high-throughput cellular baseband modems, transceiver link controllers, and complex IP architectures including Bus Fabric, NOC, AHB, and AXI. You will solve problems related to 4G/5G physical layer operations and low-power architectures for advanced SoC designs.

Skills

UVM System Verilog Python C++ System C SVA coverage driven verification LLM RTL Simulation 4G/5G 3GPP AXI AHB NoC Perl Prompt Engineering

What you'll do

Construct detailed test plans including use cases and coverage targets from design specifications.
Architect reusable UVM-based test benches featuring stimulus, checkers, VIPs, and reference models.
Develop coverage-driven verification plans to ensure all functional requirements are met.
Implement test plans from RTL simulation bring-up through final sign-off.
Identify, report, and debug failures during the verification process.
Maintain regression suites and track progress against coverage metrics.
Integrate LLMs and ML-driven workflows to improve verification efficiency and quality.

What we're looking for

Bachelor of Science degree required.
Minimum of 10 years of relevant industry experience.
Strong knowledge of System Verilog and UVM.
Proficiency in System C, C/C++, Python, and Perl.
Experience with constraint random testing, SVA, and coverage-driven verification.
Experience using LLMs and MCPs to enhance verification processes and productivity.
Experience developing Python-based automation solutions.
Knowledge of 4G/5G cellular physical layer operation (3GPP) and bus architectures like AXI or AHB is preferred.

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