Design Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $126,800–$220,900 / yr
Posted: 58 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $184k

This role $174k

$116k most similar roles pay here $232k

This role pays less than 56% of similar roles. Most pay $158,762–$209,750 — the shaded band above. At the midpoint, this role pays about $174k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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As a Design Verification Engineer at the senior level within our silicon design group, you will play a pivotal role in verifying innovative high-throughput cellular baseband modems and RF link controllers for Apple's SOCs. Your daily tasks will include crafting comprehensive UVM verification environments, developing coverage-driven test cases, and collaborating with multi-functional teams to ensure tape-out readiness. You will leverage Large Language Models (LLMs) and machine learning techniques to enhance verification processes, improve efficiency, and maintain regressions while reporting progress against coverage metrics. The ideal candidate possesses hands-on experience in ASIC design verification using UVM methodologies, proficiency in System Verilog, C/C++, Python, and Perl, and a deep understanding of constraint random testing and SVA. This role offers the opportunity to work on cutting-edge cellular systems that impact millions of users globally, advancing your expertise in complex IP architectures and low-power design verification practices.

Skills

SystemVerilog UVM Python C++ Perl LLMs MCPs SVA CI/CD 4G/5G 3GPP AHB AXI Docker Git

What you'll do

Construct detailed test plans for design components through collaboration with multi-functional teams.
Create coverage-driven verification plans from specifications, refining them to meet coverage targets.
Architect UVM-based, reusable test benches including stimulus, checkers, VIPs and reference models.
Leverage Large Language Models (LLMs) to enhance verification processes, improving efficiency and quality.
Design and implement ML-driven workflows that increase team productivity and overall verification quality.

What we're looking for

Experience with System Verilog and Universal Verification Methodology (UVM)
Hands-on ASIC design verification experience using reusable methodologies
Proficiency in C/C++, Python, Perl for automation and scripting
Ability to develop and implement DV methodologies and test plans
Knowledge of constraint random testing, SVA, and coverage-driven verification
Experience with large language models (LLMs) to enhance verification processes
Understanding of 4G/5G cellular physical layer operation (3GPP)

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