This role pays more than
54%
of similar roles. Most pay
$159,750–$216,250
— the shaded band above.
At the midpoint, this role pays about
$177k
versus about
$188k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
1984 open roles
on FindRole.
Listed pay typically runs
$175,000–$277,600
across 1590 roles with salary data.
As a Design Verification Engineer, you will join the silicon design group to ensure the quality and reliability of next-generation cellular systems. You will be responsible for constructing detailed test plans, creating coverage-driven verification plans from specifications, and architecting reusable UVM-based test benches featuring components like stimulus, checkers, VIPs, and reference models. Your daily work involves implementing test plans from RTL simulation bring-up to sign-off while managing regressions and reporting progress against coverage metrics. You will utilize SystemVerilog, UVM, SystemC, C/C++, Python, Perl, and SVA to validate complex IP and subsystem designs. Additionally, you will leverage Large Language Models and ML-driven workflows to enhance verification efficiency. This role focuses on the technical challenges of high-throughput cellular baseband modems, transceiver link controllers, and advanced fabric protocols like AXI and AHB.
UVM
System Verilog
Python
C++
System C
SVA
coverage driven verification
Constraint Random Testing
LLM
Prompt Engineering
RTL Simulation
4G
5G
3GPP
AXI
AHB
NoC
Bus Fabric
Automation
System Verilog
UVM
C
C++
Python
Perl
EDA Tools
Digital Design
Computer Architecture
ASIC
High-speed Interface Protocols
Simulation
Regression Analysis
Functional Coverage
Constrained Random Verification