Design Verification Engineer

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Melbourne, FL
Posted: 13 days ago
Freshness: Confirmed live yesterday
Nearby: 38 roles within 25 mi

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How this pay compares to similar roles

Similar $188k

$126k most similar roles pay here $230k

This listing doesn't post a salary. Most similar roles pay $159,562–$216,062.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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As a Design Verification Engineer, you will join the hardware team to ensure bug-free first silicon for SoC and IP designs. You will be responsible for all phases of pre-silicon verification, including establishing methodologies, developing test plans based on micro-architecture, and building scalable, portable verification environments. Your daily work involves creating stimulus, checkers, assertions, and trackers while managing coverage and sign-off for RTL freeze and tape-out. To achieve these goals, you will utilize SystemVerilog, UVM, and scripting languages like Python, Perl, or TCL. You will also leverage LLMs to improve execution efficiency and quality. The role involves debugging test failures, performing gate level simulations, and potentially utilizing power-aware methodologies, formal verification, or emulation techniques to solve complex hardware integration challenges within the product development lifecycle.

Skills

SystemVerilog UVM Python TCL Perl LLM Gate Level Simulation UPF PCIe USB DDR Formal Verification Emulation Simulators Waveform Viewers RTL

What you'll do

Develop detailed test and coverage plans based on micro-architecture specifications.
Establish scalable and portable verification methodologies for specific IP designs.
Build verification environments including stimulus, checkers, assertions, and trackers in SystemVerilog/UVM.
Execute design bring-up and regression testing to identify and fix hardware bugs.
Track and report verification progress using metrics such as bug counts and coverage.
Utilize LLMs and related technologies to improve verification efficiency and quality.
Perform pre-silicon verification activities to ensure bug-free first silicon for tape-out.

What we're looking for

Bachelor of Science degree in a technical subject area.
Minimum of 10 years of relevant industry experience.
Deep knowledge of Object-Oriented Programming (OOP), SystemVerilog, and UVM.
Experience developing scalable and portable test-benches.
Proficiency with verification tools including simulators, waveform viewers, and coverage collection.
Experience using Large Language Models (LLMs) to improve verification efficiency and quality.
Knowledge of scripting languages such as Python, Perl, or TCL.
Familiarity with power-aware (UPF) methodologies, serial protocols (PCIe/USB), formal verification, or emulation technologies.