Design Verification Engineer

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $150,400–$225,300 / yr
Posted: 14 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $201k

This role $188k

$140k most similar roles pay here $245k

This role pays more than 50% of similar roles. Most pay $168,500–$233,050 — the shaded band above. At the midpoint, this role pays about $188k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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The Design Verification Engineer joins the hardware team to perform design verification of Analog and Mixed Signal ASIC IPs, ensuring bug-free first silicon for System on a Chip components. The role involves developing detailed test and coverage plans based on micro-architecture, creating scalable verification environments including stimulus, checkers, assertions, and trackers. Responsibilities include executing verification plans, performing design bring-up, enabling regressions, and debugging test failures to ensure correct ASIC manufacturing. Candidates will develop block, IP, and SoC level test-benches for camera interface and usb3 controller interfaces. Essential skills include Verilog, SystemVerilog, UVM, Python, and Perl scripting. The role requires expertise in computer architecture, constrained randomization, functional/code coverage, and assertion methodology using industry standard tools like Synopsys VCS, Verdi, or Indago to validate pre-silicon use cases for soft IP cores and GPU sub-systems.

What does a Design Verification Engineer earn in California?

Median $190598 from 33 postings across 7 companies.

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Skills

System Verilog UVM Verilog Python Perl VCS Verdi Indago Assertion Methodology Constrained Randomization Code Coverage Digital Design Computer Architecture ASIC SoC USB3 Mixed Signal

What you'll do

Verify Analog and Mixed Signal ASIC IPs to ensure bug-free first silicon for SoCs.
Develop detailed test and coverage plans based on specific micro-architectures.
Create scalable and portable verification methodologies suitable for the IP.
Build verification environments including stimulus, checkers, assertions, trackers, and coverage.
Execute verification plans including design bring-up, regression enabling, and debugging of test failures.
Develop block, IP, and SoC level test-benches for camera and USB3 controller interfaces.
Track and report progress using metrics such as bug counts and coverage percentages.
Create validation scripts using Python and Perl to automate verification processes.

What we're looking for

Master's degree or foreign equivalent in Electrical Engineering, Computer Engineering, or a related field.
Experience using Verilog and SystemVerilog to create complex verification environments for pre-silicon use cases.
Knowledge of digital design and verification basics to test designs and debug failures.
Proficiency in Python to create validation scripts.
Understanding of Computer Architecture to analyze soft IP cores and GPU sub-system interoperability.
Experience using UVM (Universal Verification Methodology) in verification environments.
Ability to use scripting languages like Perl to create executable scripts.
Experience with industry standard simulation and debugging tools such as VCS, Verdi, or Indago.