Design Verification Engineer

Apple Inc

Confirmed live 2 days ago Trusted

Quick summary

Work type: On-site
Location: Cary, NC
Posted: 13 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $188k

$126k most similar roles pay here $230k

This listing doesn't post a salary. Most similar roles pay $159,562–$216,062.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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As a Design Verification Engineer, you will join the hardware team to ensure bug-free first silicon for SoC and IP designs. You will be responsible for all phases of pre-silicon verification, including establishing methodologies, developing test plans based on micro-architecture, and creating scalable, portable verification environments. Your daily work involves building infrastructure with stimulus, checkers, assertions, and trackers while managing coverage and sign-off for RTL freeze and tape-out. You will execute design bring-up, run regressions, and debug failures using SystemVerilog and UVM. The role requires proficiency in Python, Perl, or TCL, along with experience in gate level simulations, waveform viewers, and power-aware verification. Additionally, you will utilize LLMs to improve execution efficiency and quality while ensuring the reliability of complex components like PCIe, USB, or DDR protocols.

Skills

SystemVerilog UVM Python TCL Perl LLM Gate Level Simulation UPF PCIe USB DDR Formal Verification Emulation Coverage Collection Waveform Viewers RTL

What you'll do

Develop detailed test and coverage plans based on the micro-architecture of SoC/IP designs.
Establish scalable and portable verification methodologies suitable for specific IP requirements.
Build verification environments including stimulus, checkers, assertions, trackers, and coverage components.
Execute design bring-up and DV environment bring-up to ensure functional first silicon.
Debug test failures and resolve bugs identified during regression testing.
Track and report verification progress using metrics such as bug counts and coverage percentages.
Utilize LLMs and related technologies to improve verification efficiency and quality.

What we're looking for

Bachelor's degree in a technical subject area.
Minimum of 10 years of relevant industry experience.
Deep knowledge of Object-Oriented Programming (OOP), SystemVerilog, and UVM.
Experience developing scalable and portable test-benches.
Proficiency with verification tools including simulators, waveform viewers, and coverage collection.
Experience using Large Language Models (LLMs) for verification efficiency and quality.
Knowledge of scripting languages such as Python, Perl, or TCL.
Familiarity with power-aware (UPF) methodologies, formal verification, or emulation technologies.