Senior Security IP Engineer

Microsoft

Confirmed live today Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
—
Salary
$119,800–$234,700 / yr
Posted
1 day ago
Freshness
Confirmed live today
Closes
Apr 26, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $183k
This role $177k
$106k $248k
below market most similar roles pay here above market

This role pays less than 52% of similar roles. Most pay $149,875–$216,000 — the blue band above. At the midpoint, this role pays about $177k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 692 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 649 roles with salary data.

Most-posted roles

View all roles at Microsoft

At a glance

TL;DR · Senior Security IP Engineer

Role Posting Log in to save

The Senior Security IP Engineer joins the SCIPS team within the Compute Silicon & Manufacturing Engineering organization to support Microsoft’s cloud hardware infrastructure. This role involves owning the end-to-end development of security IPs, from architecture and microarchitecture definition through silicon validation. Key responsibilities include developing high-performance, power-efficient RTL designs, driving PPA optimization, and leading design signoff activities such as CDC, RDC, LINT, synthesis, and STA. The engineer will implement hardware security technologies like cryptographic accelerators, root-of-trust, secure boot, and key management. Required technical skills include proficiency in Verilog, System Verilog, and scripting languages like Python or Perl, alongside knowledge of AMBA AXI protocols. The work focuses on solving hardware manufacturing and quality challenges for state-of-the-art computer chips like Azure Cobalt.

Skills

RTL System Verilog Verilog Python Perl AMBA AXI Static Timing Analysis CDC RDC LINT Synthesis PPA Optimization Cryptography AES SHA Elliptic Curve Cryptography root-of-trust Secure Boot Silicon Validation Post-silicon Debug

What you'll do

  • Own end-to-end development of security IPs from architecture definition through silicon validation.
  • Develop high-performance, power-efficient RTL designs and drive PPA optimization across the design lifecycle.
  • Lead design signoff activities including CDC, RDC, LINT, synthesis, STA, and timing closure.
  • Implement hardware security technologies such as cryptographic accelerators, root-of-trust, secure boot, and key management.
  • Drive pre-silicon and post-silicon debug, silicon bring-up, and root-cause analysis of complex system issues.
  • Mentor engineers and champion design excellence through reviews, automation, and continuous methodology improvements.

What we're looking for

  • Must have a Doctorate and 1+ years of experience, a Master's and 4+ years of experience, or a Bachelor's and 5+ years of experience in a related field.
  • Must be able to pass the Microsoft Cloud Background Check every two years.
  • Must provide proof of citizenship or US residency to access information controlled for export under various regulations.
  • 8+ years of hardware design experience (preferred).
  • Expertise in Digital Design including microarchitecture specification development and RTL coding (preferred).
  • Expertise in Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and LINT closure (preferred).
  • Proficiency in Verilog, System Verilog, and scripting languages such as Python or Perl (preferred).
  • Export control regulations.

Related searches

More Senior Security IP Engineer jobs All jobs at Microsoft

More like this

Similar roles

Senior Security IP Design Engineer

Arm Holdings

Austin, TX +2 85 days ago $161,500–$218,500
Verilog RTL SystemVerilog UVM OVM SoC Architecture Applied Cryptography Secure Boot Key Management AXI AHB Python Perl TCL UPF CDC RDC LINT Timing Analysis Synthesis Hardware Root of Trust
Hybrid
Save

Senior Security IP Design Engineer

Arm Holdings

Austin, TX +2 85 days ago $161,500–$218,500
Verilog RTL SystemVerilog UVM OVM SoC Architecture Applied Cryptography Secure Boot Key Management AXI AHB Python Perl TCL UPF CDC RDC LINT Timing Analysis Synthesis Hardware Root of Trust
Hybrid
Save

Senior Silicon Design Engineer

Microsoft

15 days ago $119,800–$234,700
RTL SystemVerilog Verilog VHDL Python Perl C/C++ C# AMBA AXI Static Timing Analysis Synthesis CDC RDC LINT LEC Microarchitecture Post-Silicon Validation PPA Optimization
5+ yrs exp Hybrid
Save

Senior FPGA/Silicon Design Engineer

Microsoft

16 days ago $119,800–$234,700
FPGA RTL SystemVerilog Verilog VHDL Python Microarchitecture CDC RDC LINT LEC Synthesis Xilinx ChipWhisperer PPA Optimization Post-Silicon Validation Test Automation
5+ yrs exp Hybrid
Save

Senior Logic Design Engineer

Microsoft

13 days ago $119,800–$234,700
RTL Verilog System Verilog Static Timing Analysis SDC Synthesis Physical Design DFT Python Tcl Perl UPF Lint CDC Low Power Analysis Formal Equivalence Verification ARM SoC Design
5+ yrs exp Hybrid
Save

Senior IP Verification Engineer

Arm Holdings

Chandler, AZ 99 days ago $161,500–$218,500
Questa VCS Jasper Gold Verdi Python Perl UPF JTAG TAP DFT RTL Functional Verification Static Simulation Dynamic Simulation Object-Oriented Programming
Hybrid
Save