Senior Logic Design Engineer

Microsoft

Confirmed live today Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
—
Salary
$119,800–$234,700 / yr
Posted
11 days ago
Freshness
Confirmed live today
Closes
Apr 14, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k
This role $177k
$106k $248k
below market most similar roles pay here above market

This role pays less than 53% of similar roles. Most pay $167,212–$216,250 — the blue band above. At the midpoint, this role pays about $177k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 694 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 651 roles with salary data.

Most-posted roles

View all roles at Microsoft

At a glance

TL;DR · Senior Logic Design Engineer

The Senior Logic Design Engineer joins the Silicon Logic Design team within the Compute Silicon & Manufacturing Engineering organization to support Microsoft’s cloud hardware infrastructure. This role focuses on driving high-quality RTL toward Physical Design handoff, with a specific emphasis on static timing analysis, SDC constraints, and synthesis correlation. Key responsibilities include designing and maintaining robust timing constraints, performing quality assurance for PD and STA consumption, and analyzing synthesis results to achieve PPA targets. The engineer will develop functional block RTL, perform design quality checks like Lint and CDC, and automate tasks using scripting. Required technical skills include Verilog, SystemVerilog, and scripting in Perl, Tcl, or Python. The work involves solving complex hardware manufacturing and optimization problems for state-of-the-art computer chips like Azure Cobalt.

What you'll do

  • Design, develop, and maintain robust timing (SDC) constraints for functional correctness and PPA targets.
  • Generate constraints and perform quality assurance for Physical Design and Static Timing Analysis consumption.
  • Analyze and debug synthesis results to drive RTL optimization toward performance and power goals.
  • Develop and integrate various functional block RTL for IP and SoC levels.
  • Perform design quality checks including Timing closure, Lint, CDC, and Low Power Intent.
  • Automate engineering tasks and processes using scripting languages like Python, Perl, or Tcl.
  • Write basic tests to exercise block functionality and debug features at the IP and SoC levels.
  • Mentor team members and summer interns to support the growth of the engineering team.

What we're looking for

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of technical engineering experience.
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of technical engineering experience.
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of technical engineering experience.
  • Equivalent experience to the degree and years of experience requirements.
  • Ability to pass the Microsoft Cloud Background Check and meet government security screening requirements.
  • Ability to provide proof of citizenship or US residency to access export-controlled information.
  • Experience in static timing analysis and logic domain including SDC/Timing Constraint generation, analysis, and quality assurance (preferred).
  • Experience with synthesis script setup, debug, analysis, and drive to quality targets (preferred).

More like this

Similar roles

Logic Design Engineer

Microsoft

6 days ago $102,100–$202,200
Verilog System Verilog RTL Logic Design Synthesis Timing Closure Lint CDC UPF Low Power Analysis Formal Equivalence Verification Power Analysis ARM Scripting VCLP Verilog Simulators
2+ yrs exp Hybrid

AI/ML Logic Design Engineer-Senior

Qualcomm

Austin, TX 40 days ago $133,900–$200,900
SystemVerilog RTL Design Python Perl Shell Scripting Logic Synthesis Static Timing Analysis AI/ML Git Microarchitecture Instruction Set Architecture Digital Design
2+ yrs exp

Senior Circuit Design Engineer

Nvidia

Santa Clara, CA 62 days ago
Circuit Design Mixed-Signal Analog Digital Circuit Design Spice EM/IR Analysis Static Timing Analysis RTL Logic Synthesis Place and Route Design-for-test (DFT) Perl Tcl Make Monte-Carlo ADC Op-Amp Hardware Security
8+ yrs exp Hybrid

Senior Circuit Design Engineer

Nvidia

Santa Clara, CA 103 days ago
Circuit Design Standard Cell Characterization SPICE Python Perl Tcl Make Liberty Models OCV Digital Implementation Signoff Flows Automation Deep Submicron Process
4+ yrs exp

Senior Circuit Design Engineer

Nvidia

Santa Clara, CA 92 days ago $136,000–$218,500
Circuit Design Standard Cell ROM SPICE Perl Tcl Make DRC LVS EM/IR SRAM Flip Flops Level Shifters Deep Submicron Layout Simulation Scripting Automation
5+ yrs exp

Senior Circuit Design Engineer

Nvidia

Santa Clara, CA 8 days ago $136,000–$218,500
Circuit Design RTL Layout Spice EM/IR Analysis Static Timing Analysis PnR Logic Synthesis Python Perl Tcl Make Power Gating DRC LVS Post-Silicon Characterization Hardware Security AI/ML
5+ yrs exp Hybrid