Senior Principal ASIC FPGA Engineer

General Dynamics

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Boise, ID
Salary
$191,146–$212,053 / yr
Posted
50 days ago
Freshness
Confirmed live yesterday
Nearby
49 roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $193k
This role $202k
$142k most similar roles pay here $228k

This role pays more than 60% of similar roles. Most pay $170,000–$216,250 — the shaded band above. At the midpoint, this role pays about $202k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About General Dynamics

General Dynamics is a global aerospace and defense company offering a broad portfolio of products and services in business aviation, ship construction, land combat vehicles, and information technology. It serves customers in the U.S. government, allied governments, and a diverse array of commercial markets.

General Dynamics currently has 1123 open roles on FindRole.

Listed pay typically runs $124,093–$150,385 across 984 roles with salary data.

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At a glance

TL;DR · Senior Principal ASIC FPGA Engineer

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As a Senior Principal ASIC FPGA Engineer, you will join the engineering team to provide technical leadership throughout the full ASIC design lifecycle. You will own the architecture by defining technical approaches from concept through silicon, including system partitioning and microarchitecture. Your daily responsibilities include leading RTL development for bus fabric integrity, clock domain crossings, and reset sequencing, while managing timing closure at advanced FinFET process nodes. You will oversee verification activities, conduct code reviews, manage JIRA triages, and contribute to program planning via Integrated Master Schedules. The role requires expertise in RTL design, synthesis flows, power analysis, and EDA tools for simulation and formal verification. You will solve complex hardware challenges by navigating the transition from high-level design to GDSII, ensuring robust performance across advanced manufacturing nodes like 7nm or 5nm.

Skills

ASIC FPGA RTL Microarchitecture Synthesis Static Timing Analysis Clock Domain Crossing DFT GDSII FinFET EDA Tools JIRA Power Analysis Tape-out Verification

What you'll do

  • Define ASIC/FPGA technical approaches including system partitioning, microarchitecture, and interface definitions from concept to silicon.
  • Lead RTL development focusing on bus fabric integrity, clock domain crossings, and reset order-of-operations.
  • Resolve complex timing closure issues during synthesis, place and route, and static timing analysis at advanced nodes.
  • Serve as the primary point of contact for verification activities and develop rigorous test and simulation plans.
  • Manage JIRA triage to prioritize work items and ensure the backlog reflects program reality.
  • Conduct RTL code reviews to set technical standards and provide feedback to engineers across all levels.
  • Provide technical input for Integrated Master Schedule development, Earned Value reporting, and proposal support.
  • Evaluate foundry technologies, device libraries, IP cores, and EDA tools to inform design decisions.

What we're looking for

  • Bachelor's degree in Electrical or Computer Engineering, or a related field, plus 10 years of experience; or a Master's degree plus 8 years of experience.
  • U.S. citizenship is required.
  • Ability to obtain a Department of Defense Secret security clearance.
  • 10-15+ years of ASIC/FPGA design experience as an RTL designer.
  • Proven experience taking designs through full ASIC tape-out, including timing closure and post-silicon bring-up.
  • Expertise in RTL design, microarchitecture, bus fabric, clock domain crossing (CDC), and reset sequencing.
  • Experience with FinFET process nodes (7nm, 5nm) and commercial foundry flows is a meaningful differentiator.
  • Proficiency in industry-standard EDA tools for synthesis, simulation, formal verification, and STA.

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