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SystemVerilog UVM Python C AI-assisted coding tools RTL code EDA vendor tools Synopsys Cadence Mentor +5 more Show less

UVM SystemVerilog constraint-random verification coverage-driven sign-off Artificial Intelligence tools NPUs image/video processing pipelines custom silicon architectures Synopsys front-end suites MIPI RTL VHDL CI/CD Git +9 more Show less

SystemVerilog UVM Perl Python Veloce Palladium Zebu HAPS IEV VC Formal PCIe CXL Ethernet RDMA DDR TCP +11 more Show less

SystemVerilog UVM C++ Python Perl TCL DSP QAM Formal Verification Jasper VCFormal CI/CD Git Linux +9 more Show less

SystemVerilog UVM C++ PCIe CXL ARM AMBA Python CI/CD MentorGraphicsCalibre SynopsysVCS Linux Git Docker Jenkins GitHub GoogleCloudPlatform AzureDevOps AItools +14 more Show less

SystemVerilog UVM Linux C++ Python Perl Veloce Palladium Zebu HAPS CI/CD Networking Dashboard_management Emulation_platforms +9 more Show less

UVM System Verilog Python Coherent Hub Interface (CHI) cache coherency architectures Universal Verification Methodology (UVM) System Verilog Test Bench (SVTB) generative AI C++ Perl Tcl +6 more Show less

C C++ Python Perl VCS emulation FPGA debugging_tools shell +4 more Show less

SystemVerilog C++ Python Ruby Perl UVM OVM SystemVerilog_Test_Bench(SVTB) Formal_Verification CI/CD Git JIRA Microsoft_Teams +8 more Show less

Verilog SystemVerilog UVM SVA VCS Perl Tcl Makefiles Python LLMs Agentic AI frameworks VCS-XA Gate Level Simulation Formal Equivalence +9 more Show less

SystemVerilog UVM SystemVerilog-UVM C++ C Perl Python VHDL Verilog AMBA_Bus_Protocol Formal_Verification Assertion_Based_Formal_Verification +7 more Show less

SystemVerilog UVM C++ Python Perl Shell scripting VCS Debussy GDB ASIC verification dynamic memory controllers ddr2 ddr3 ddr4 ddr5 lpddr2 lpddr3 lpddr4 lpddr5 lpddr6 HBM GDDR +17 more Show less

Verilog SystemVerilog Python Perl RTL simulation waveform debug digital design logic design concepts +3 more Show less

SystemVerilog UVM C++ Python PCIe CXL CHI VCS Debussy GDB +5 more Show less

SystemVerilog UVM OVM Python MATLAB C C++ Perl Ruby Analog Mixed-Signal (AMS) DFT Kubernetes Azure CI/CD Git JIRA PostgreSQL MESON +13 more Show less

Python AI ML EDA LLMs Data Science Power Modeling Transistor Device Physics System-Level Optimization Silicon Validation HW-SW Co-Design CPU/GPU/SoC Architecture Codesign Engineering Post-Silicon Bring-Up Frequency and Power Characterization +10 more Show less

SystemVerilog UVM Python Perl C++ VHDL Verilog SystemC AI ML GenAI 4G/5G 3GPP Formal verification Simulation acceleration Unix/Linux Makefiles XML OOP HW/SW co-verification +15 more Show less

SystemVerilog UVM Assertions C++ Python DDR CACHE SOC Formal verification PASIM simulations Memory verification VIPs +6 more Show less

C++ ISO C++20/23/26 NVIDIA test frameworks Test automation Software Development Lifecycle (SDLC) High-Performance Computing (HPC) Software Testing Methodologies Git Perforce JIRA Make LLM technologies ARM64 X64 RISC-V +10 more Show less

SystemVerilog Object-Oriented Programming Python C++ Docker Git CI/CD Linux VCS DVMS UVM SVUnit Perl Makefile Doxygen JIRA Confluence +12 more Show less