Senior FPGA Verification Engineer, Air Dominance and Strike

Anduril Industries

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Costa Mesa, CA
Salary: $166,000–$220,000 / yr
Posted: 9 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $188k

This role $193k

$137k most similar roles pay here $229k

This role pays more than 68% of similar roles. Most pay $166,912–$209,575 — the shaded band above. At the midpoint, this role pays about $193k versus about $188k for comparable roles.

Based on 240 similar postings.

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About Anduril Industries

Anduril Industries is a defense technology company that builds advanced hardware and software systems for national security, including autonomous drones, surveillance systems, and the Lattice AI command platform.

Anduril Industries currently has 1697 open roles on FindRole.

Listed pay typically runs $146,000–$194,000 across 1504 roles with salary data.

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At a glance

TL;DR · Senior FPGA Verification Engineer, Air Dominance and Strike

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As a Senior FPGA Verification Engineer, you will join the team to own the verification of FPGA/SoC designs on AMD Xilinx platforms for flight-critical avionics. You will architect and implement UVM verification environments, including drivers, monitors, predictors, and scoreboards, while developing verification plans with traceability to system requirements. Your daily work involves authoring SystemVerilog Assertions for protocol compliance, building functional coverage models, and creating constrained-random test sequences to uncover corner-case bugs. You will also manage regression suites, debug failures using waveform tools, and collaborate on RTL reviews and micro-architecture refinements. The role requires expertise in SystemVerilog, UVM methodology, object-oriented programming, and industry simulators like Questa or Vivado. You will ensure designs meet DO-254 safety standards while solving complex technical challenges inherent in high-stakes avionics development for unmanned systems.

Skills

SystemVerilog UVM SVA FPGA SoC Xilinx Python Tcl Makefile Git Linux CI/CD Ethernet PCIe JESD204C MIL-STD-1553 SPI Questa VCS Xcelium Vivado

What you'll do

Architect and implement UVM verification environments for AMD Xilinx FPGA/SoC designs.
Develop verification plans with traceability to specific system and hardware requirements.
Author SystemVerilog Assertions (SVA) to ensure protocol compliance and design intent.
Build functional coverage models and drive code coverage analysis to completion.
Create constrained-random and transaction-level test sequences to identify corner-case bugs.
Manage regression suites while tracking coverage metrics and verification progress.
Debug hardware and software failures using waveform tools and simulation logs.
Ensure all verification processes comply with DO-254 and other safety standards.

What we're looking for

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
8+ years of experience in FPGA/ASIC verification.
Proficiency in SystemVerilog, UVM methodology, and SystemVerilog Assertions (SVA).
Experience with object-oriented programming principles.
Experience using industry simulators such as Questa, VCS, Xcelium, or Vivado.
Experience working in Linux development environments and Git-based collaborative workflows.
Eligibility to obtain and hold a U.S. Secret security clearance.

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