Senior FPGA Verification Engineer, Air Dominance and Strike

Anduril Industries

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Quick summary

Work type
On-site
Location
Costa Mesa, CA
Salary
$166,000–$220,000 / yr
Posted
55 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $188k
This role $193k
$135k $229k
below market most similar roles pay here above market

This role pays more than 66% of similar roles. Most pay $162,000–$214,000 — the blue band above. At the midpoint, this role pays about $193k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Anduril Industries

Anduril Industries is a defense technology company that builds advanced hardware and software systems for national security, including autonomous drones, surveillance systems, and the Lattice AI command platform.

Anduril Industries currently has 901 open roles on FindRole.

Listed pay typically runs $166,000–$220,000 across 858 roles with salary data.

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At a glance

TL;DR · Senior FPGA Verification Engineer, Air Dominance and Strike

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The Senior FPGA Verification Engineer joins the Air Dominance and Strike team to own the verification of FPGA/SoC designs on AMD Xilinx platforms for flight-critical avionics. The role involves architecting and implementing UVM verification environments, including drivers, monitors, predictors, and scoreboards. Key responsibilities include developing verification plans with hardware requirement traceability, authoring SystemVerilog Assertions for protocol compliance, and building functional coverage models. The engineer will develop constrained-random test sequences, maintain regression suites, and debug failures using waveform tools. Required technical skills include SystemVerilog, UVM methodology, object-oriented programming, and experience with industry simulators like Questa, VCS, Xcelium, or Vivado. The work focuses on rapid avionics development, ensuring compliance with DO-254 safety standards for complex aerospace hardware systems.

Skills

SystemVerilog UVM SVA FPGA SoC AMD (Xilinx Python Tcl Makefile Git Linux Questa VCS Xcelium Vivado CI/CD Ethernet PCIe JESD204C MIL-STD-1553 SPI DO-254

What you'll do

  • Architect and implement UVM verification environments for AMD Xilinx FPGA/SoC designs.
  • Develop verification plans with full traceability to system and hardware requirements.
  • Author SystemVerilog Assertions for protocol compliance and design intent checks.
  • Build functional coverage models and drive code coverage analysis to closure.
  • Develop constrained-random and transaction-level test sequences to uncover corner-case bugs.
  • Debug failures using waveform tools and simulation logs at the HDL and system levels.
  • Support hardware validation and board bring-up on target platforms.
  • Ensure all verification processes meet DO-254 and relevant safety standards.

What we're looking for

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 8+ years of experience in FPGA/ASIC verification.
  • Proficiency in SystemVerilog, UVM methodology, and SystemVerilog Assertions (SVA).
  • Experience with object-oriented programming principles and Linux development environments.
  • Experience with industry simulators such as Questa, VCS, Xcelium, or Vivado.
  • Ability to obtain and hold a U.S. Secret security clearance.
  • Master’s degree in Electrical Engineering, Computer Engineering, or a related field (preferred).
  • 12+ years of experience in FPGA/ASIC verification (preferred).

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