Senior DFT Engineer

Nvidia

Confirmed live 2 days ago High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$136,000–$218,500 / yr
Posted
7 days ago
Freshness
Confirmed live 2 days ago

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k
This role $177k
$126k most similar roles pay here $228k

This role pays more than 55% of similar roles. Most pay $158,825–$214,800 — the shaded band above. At the midpoint, this role pays about $177k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior DFT Engineer

As a Senior DFT Engineer, you will join the Design-for-Test Engineering team to develop and deploy state-of-the-art methodologies for next-generation products. You will own cross-functional projects involving test access mechanisms, IO BIST, memory BIST, and scan compression while mentoring junior engineers on test designs and trade-offs regarding cost and quality. Your daily work involves defining scan test plans, fault modeling, ATPG, and fault simulation for complex multi-million gate designs. You will utilize vendor tools to verify test patterns and logic while collaborating with teams across RTL, clocks design, STA, place-n-route, and power. The role requires expertise in silicon debug and bring-up on ATE using pattern formats and failure processing. Required skills include proficiency in Perl, Python, or Tcl to solve technical challenges within the semiconductor chip domain.

What you'll do

  • Implement state-of-the-art designs in test access mechanisms, IO BIST, memory BIST, and scan compression.
  • Develop and deploy DFT methodologies for next-generation products.
  • Define scan test plans, fault modeling, ATPG, and fault simulation.
  • Verify and validate test patterns and logic on complex multi-million gate designs using vendor tools.
  • Perform silicon debug and bring-up on ATE with an understanding of pattern formats and failure processing.
  • Develop test programs and utilize scripting in Perl, Python, or Tcl for automation.
  • Mentor junior engineers on test designs and trade-offs regarding cost and quality.

What we're looking for

  • A BSEE with experience, an MSEE with experience, or a PhD in DFT or related domains is required.
  • Demonstrated expertise in scan test plans, BIST (memory and IO), fault modeling, ATPG, and fault simulation is required.
  • Analytical skills in verification and validation of test patterns and logic on multi-million gate designs using vendor tools are required.
  • Experience with cross-functional areas including RTL, clock design, STA, place-and-route, and power is required.
  • Experience in silicon debug and bring-up on ATE with knowledge of pattern formats and test program development is required.
  • Proficiency in programming and scripting using Perl, Python, or Tcl is desired.
  • Excellent written and oral communication skills are required.

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