Senior DFT Engineer

Nvidia

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Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAAustin, TX
Employment: Full-time
Posted: 49 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior DFT Engineer

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The Senior DFT Engineer joins the DFX team to shape the future of compute by stewarding the entire Scan Test Lifecycle for advanced silicon. This role involves designing and prototyping breakthrough Test Architectures for reticle sized, multi-chiplet products, including 2.5D/3D AI data center platforms, Gaming and Enterprise GPUs, and complex SOCs. Key responsibilities include developing industry-leading test methodologies, owning the full ATPG lifecycle from verification to ATE bring-up, and co-architecting novel DFT strategies with VLSI and Product Engineering teams. The candidate must utilize industry standard ATPG tools and collaborate with EDA vendors to drive scalable, automated solutions. Required expertise includes deep knowledge of DFT tools and methodologies for large-scale designs, along with experience in silicon testing and Automatic Test Equipment.

Skills

DFT ATPG ATE VLSI Scan Test RTL Verification Post-Silicon 2.5D/3D ICs Multi-chiplet AI CAD

What you'll do

Develop and deploy industry-leading test methodologies on next-generation silicon platforms.
Partner with EDA vendors and internal CAD teams to develop scalable, automated tool solutions.
Co-architect novel DFT strategies with VLSI and Product Engineering teams for silicon innovation.
Own the full ATPG lifecycle including verification, coverage analysis, pattern generation, and ATE bring-up.
Design and prototype test architectures for reticle-sized, multi-chiplet products from RTL to post-silicon.
Guide and mentor junior engineers on complex design trade-offs to ensure quality and efficiency.

What we're looking for

MS/PhD or equivalent experience in Electrical Engineering or a related field.
6+ years of hands-on experience in Design-For-Test (DFT).
Deep knowledge of DFT tools, methodologies, and test strategies for complex, large-scale designs.
Strong experience with industry standard ATPG tools.
Clear and effective written and verbal communication skills.
Passion for mentoring and scaling technical excellence in a team.
Experience with 2.5D/3D ICs, multi-chiplet architectures, or reticle-sized designs (preferred).
Background in developing or enhancing EDA tool flows (preferred).

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