Senior DFT Engineer

Nvidia

Confirmed live yesterday Trusted

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $196,000–$310,500 / yr
Employment: Full-time
Posted: 27 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $186k

This role $253k

$123k $331k

below market most similar roles pay here above market

This role pays more than 96% of similar roles. Most pay $155,750–$216,250 — the blue band above. At the midpoint, this role pays about $253k versus about $186k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior DFT Engineer

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The Senior DFT Engineer will join the Advanced Technology Group to optimize design tradeoffs and methodology for next generation CMOS technology. This role involves managing all aspects of testing, including logic insertion, verification, test pattern generation, and test program bring-up. The engineer will also perform complex debug and failure analysis to resolve issues, design advanced packaging vehicles, and find root causes for product bring-up testing problems. Key responsibilities include balancing test time with data collection for new process nodes. Required expertise includes IEEE1149.1, IEEE1500, SSN scan compression, IOBIST, and memory BIST. Candidates must possess skills in test logic design verification, pattern generation, and ATE test program development. Technical requirements include proficiency in industry standard DFT EDA tools and programming languages like Python.

Skills

DFT CMOS IEEE1149.1 IEEE1500 SSN Scan Compression IOBIST Memory BIST ATE Python DDR HBM Failure Analysis LVP Photon Emission Ebeam Probing Advantest 93k EDA Tools Test Pattern Generation Logic Design Verification

What you'll do

Manage all aspects of testing including methodology, logic insertion, verification, and test pattern generation.
Execute test program bring-up and perform complex debug and failure analysis to resolve issues.
Optimize tradeoffs between test time and data collection for next-generation process nodes.
Design and tape out advanced packaging vehicles.
Identify root causes for product bring-up testing issues.
Develop new DFT flows and enhance existing flows using industry-standard EDA tools.
Develop ATE test programs and specify custom test methods for data collection.

What we're looking for

Hold a BS in Electrical or Computer Engineering or equivalent experience.
12+ years experience in design for test.
In-depth knowledge of test architectures including IEEE1149.1, IEEE1500, SSN scan compression, IOBIST, and memory BIST.
Expertise in test logic design verification, pattern generation, and developing or enhancing flows.
Experience in ATE test program development and bring-up, including specifying custom test methods.
Hands-on knowledge of industry standard DFT EDA tools.
Proficiency in programming and scripting languages, such as Python.
Experience with DDR and HBM high speed I/O testing (preferred).
Hands-on experience with failure analysis equipment like LVP, photon emission, and ebeam probing (preferred).
Proficiency with Advantest 93k testers (preferred).

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