Senior DFT Engineer

Nvidia

Confirmed live 2 days ago High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $196,000–$310,500 / yr
Posted: 24 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $186k

This role $253k

$124k most similar roles pay here $330k

This role pays more than 97% of similar roles. Most pay $158,987–$213,731 — the shaded band above. At the midpoint, this role pays about $253k versus about $186k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior DFT Engineer

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The Senior DFT Engineer joins the Advanced Technology Group to optimize design tradeoffs and methodology on next generation CMOS technology. This role involves managing all aspects of testing, including logic insertion, verification, test pattern generation, test program bring-up, and complex debug or failure analysis to resolve issues. The engineer will balance test time against data collection requirements for new process nodes while designing and taping out advanced packaging vehicles. Required expertise includes IEEE1149.1, IEEE1500, SSN scan compression, IOBIST, and memory BIST architectures. Candidates must possess skills in test logic design verification, pattern generation, ATE test program development, and proficiency in Python and industry standard DFT EDA tools. Additional experience with DDR and HBM high speed I/O testing, failure analysis equipment like LVP or ebeam probing, and Advantest 93k testers are highly valued for this role.

Skills

DFT IEEE1149.1 IEEE1500 SSN Scan Compression IOBIST Memory BIST ATE Python DDR HBM Failure Analysis LVP Photon Emission ebeam probing Advantest 93k

What you'll do

Manage all aspects of testing including methodology, logic insertion, verification, and test pattern generation.
Execute test program bring-up and perform complex debug/FA to resolve technical issues.
Balance trade-offs between test time and data collection for next-generation process nodes.
Design and tapeout advanced packaging vehicles as part of the engineering team.
Identify root causes for product bring-up testing issues.
Develop new flows and enhance existing DFT flow processes.
Create custom test methods to facilitate necessary data collection during ATE development.

What we're looking for

Hold a BS in Electrical Engineering, Computer Engineering, or equivalent experience.
Have 12+ years of experience in design for test (DFT).
Possess in-depth knowledge of test architectures including IEEE1149.1, IEEE1500, SSN scan compression, IOBIST, and memory BIST.
Demonstrate expertise in test logic design verification and pattern generation.
Have experience in ATE test program development, bring-up, and specifying custom test methods.
Possess hands-on knowledge of industry standard DFT EDA tools.
Be proficient in programming and scripting languages such as Python.
Experience with high speed I/O testing, failure analysis equipment, or Advantest 93k testers is preferred.

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