Senior DFT Engineer

What you'll do

• Implement state-of-the-art designs in test access mechanisms, IO BIST, memory BIST, and scan compression.
• Develop and deploy DFT methodologies for next-generation products across various product lines.
• Define and prototype high-speed test access architectures and in-system-test architectures.
• Create DFX architectures to meet system-level safety diagnostics and advanced defect screening for automotive and industrial platforms.
• Deliver efficient workflows and tools to productize features on processors for deep learning, gaming, and supercomputing.
• Perform silicon debug, bring-up, and manage the full silicon life-cycle.
• Mentor junior engineers on test designs, trade-offs, cost, and quality.

What we're looking for

• BSEE with 8+ years of experience, MSEE with 5+ years, or PhD with 3+ years in DFT or related domains.
• Demonstrated expertise in scan test plans, BIST (memory and IO), fault modeling, ATPG, and fault simulation.
• Analytical skills in verification and validation of test patterns and logic on complex, multi-million gate designs using vendor tools.
• Exposure to cross-functional areas including RTL & clocks design, STA, place-n-route, and power.
• Experience in silicon debug and bring-up on ATE with knowledge of pattern formats, failure processing, and test program development.
• Strong programming and scripting skills in Perl, Python, or Tcl (preferred).
• Excellent written and oral communication skills.