Senior DFT Engineer

Nvidia

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 5 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $186k

This role $216k

$128k $279k

below market most similar roles pay here above market

This role pays more than 80% of similar roles. Most pay $155,750–$216,250 — the blue band above. At the midpoint, this role pays about $216k versus about $186k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior DFT Engineer

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The Senior DFT Engineer joins the DFX Architecture team to develop and deploy state-of-the-art designs for test access mechanisms, IO BIST, memory BIST, and scan compression. This role involves defining and prototyping next-generation DFX architectures, including high-speed test access, in-system-test architecture, and ISO26262 functional safety diagnostics. The engineer will collaborate with cross-functional teams to productize methodologies for processors used in deep learning, gaming, HPC, and supercomputing. Key responsibilities include silicon debug, bring-up, and fault modeling for complex multi-million gate designs. Required expertise includes scan test plans, ATPG, fault simulation, and experience with RTL, clocks, STA, and place-n-route. Candidates should possess strong programming skills in Perl, Python, or Tcl to deliver efficient workflows for advanced defect screening and silicon life-cycle management.

Skills

DFT BIST Scan Compression ATPG Fault Simulation Python Perl Tcl RTL STA ASIC Design VLSI Silicon Debug ATE ISO26262 CAD

What you'll do

Implement state-of-the-art designs for test access mechanisms, IO BIST, memory BIST, and scan compression.
Develop and deploy DFT methodologies for next-generation products and high-speed test access architectures.
Define and prototype DFX architectures for in-system testing and ISO26262 functional safety diagnostics.
Craft DFX methodologies to meet system-level safety diagnostic quality and advanced defect screening for automotive and robotics platforms.
Productize new methodologies by collaborating with system architecture, ASIC design, verification, and software development teams.
Deliver efficient workflows and tools to productize features on processors for deep learning, gaming, and supercomputing.
Perform silicon debug and bring-up on ATE including pattern formats, failure processing, and test program development.
Mentor junior engineers on test designs and trade-offs regarding cost and quality.

What we're looking for

BSEE with 8+ years of experience, MSEE with 5+ years, or PhD with 3+ years in DFT or related domains.
Demonstrated knowledge and expertise in defining scan test plans, BIST for memories and IOs, fault modeling, ATPG, and fault simulation.
Excellent analytical skills in verification and validation of test patterns and logic on complex, multi-million gate designs using vendor tools.
Good exposure to cross-functional areas including RTL & clocks design, STA, place-n-route, and power.
Experience in silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development.
Strong programming and scripting skills in Perl, Python, or Tcl (preferred).
Extraordinary written and oral communication skills.

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