Senior DFT Power Methodology Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Employment: Full-time
Posted: 62 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

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At a glance

TL;DR · Senior DFT Power Methodology Engineer

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As a Senior DFT Power Methodology Engineer, you will join the Design-for-X Engineering team to innovate in DFT Power, Thermal, and Voltage Noise Methodology areas. You will develop groundbreaking low power and thermal solutions for manufacturing tests on complex semiconductor chips, specifically targeting datacenter GPUs. Your daily responsibilities include collaborating with multi-functional teams to implement new methodologies for improving outgoing chip quality, performing post-silicon data analysis for power architecture, and deploying DFT methodologies using Applied ML and Gen AI solutions. You will also mentor junior engineers on test designs and trade-offs. Required skills include expertise in DFT, VLSI power, timing, and voltage noise, along with experience in Power Analysis, Thermal Analysis, IR Drop tools, statistical data analysis, RTL, clocks design, STA, and place-n-route.

Skills

DFT VLSI Power Analysis Thermal Analysis IR Drop RTL STA ATE SLT Applied ML Gen AI Post-Silicon Debug EDA

What you'll do

Innovate in DFT Power, Thermal, and Voltage Noise Methodology areas.
Develop low power and thermal solutions for manufacturing tests on datacenter GPUs.
Implement new methodologies to improve the outgoing quality of complex semiconductor chips.
Perform post-silicon data analysis for power to architect next-generation solutions.
Develop and deploy DFT methodologies using Applied ML and Gen AI solutions.
Mentor junior engineers on test designs and cost-quality trade-offs.

What we're looking for

BSEE with , MSEE with , or PhD with experience in DFT design & power.
Understanding of fundamental DFT topics and VLSI areas of power, timing, and voltage noise.
Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route, and power.
Experience in Silicon debug and bring-up on the ATE or SLT platforms.
Excellent knowledge in using statistical tools for data analysis & insights.
Ability to think like a programmer to translate actions into AI Coding harnesses.
Experience in Power Analysis, Thermal Analysis & IR Drop tools (preferred).
Experience in application of AI for EDA-related problem-solving (preferred).

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