Senior DFT Power Methodology Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$196,000–$310,500 / yr
Posted
16 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k
This role $253k
$128k most similar roles pay here $330k

This role pays more than 93% of similar roles. Most pay $170,000–$216,250 — the shaded band above. At the midpoint, this role pays about $253k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior DFT Power Methodology Engineer

As a Senior DFT Power Methodology Engineer, you will join the Design-for-X Engineering team to innovate within the DFT Power, Thermal, and Voltage Noise Methodology areas. You will develop groundbreaking low power and thermal solutions for manufacturing tests on complex semiconductor chips, specifically targeting conditions that push the boundaries for datacenter GPUs. Your daily responsibilities include collaborating with multi-functional teams to implement new methodologies for improving chip quality, performing post-silicon data analysis for power architecture, and deploying DFT methodologies using Applied ML and Gen AI solutions. You will also mentor junior engineers on test designs and trade-offs. Required skills include expertise in VLSI areas like timing and voltage noise, experience with Power Analysis, Thermal Analysis, and IR Drop tools, as well as proficiency in statistical tools for data analysis and silicon debug on ATE or SLT platforms.

What you'll do

  • Innovate in DFT power, thermal, and voltage noise methodology areas.
  • Develop low power and thermal solutions for manufacturing tests on datacenter GPUs.
  • Perform post-silicon data analysis to architect next-generation power solutions.
  • Develop and deploy DFT methodologies using Applied ML and Gen AI solutions.
  • Mentor junior engineers on test designs and trade-offs regarding cost and quality.
  • Solve complex problems related to improving the outgoing quality of semiconductor chips.

What we're looking for

  • A BSEE with experience, an MSEE with , or a PhD with experience in DFT design and power is required.
  • Candidates must have an understanding of fundamental DFT topics and VLSI areas including power, timing, and voltage noise.
  • Experience with Power Analysis, Thermal Analysis, and IR Drop tools is preferred.
  • Experience applying AI for EDA-related problem-solving is preferred.
  • Proficiency in using statistical tools for data analysis and insights is required.
  • Candidates should have exposure to multi-functional areas including RTL, clock design, STA, place-and-route, and power.
  • Experience in silicon debug and bring-up on ATE or SLT platforms is required.
  • Strong written and oral communication skills are required to collaborate with multi-functional teams and mentor junior engineers.

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