Senior DFT Engineer

Nvidia

Confirmed live today Trusted

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Employment: Full-time
Posted: 27 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $186k

This role $177k

$124k $244k

below market most similar roles pay here above market

This role pays more than 50% of similar roles. Most pay $155,750–$216,250 — the blue band above. At the midpoint, this role pays about $177k versus about $186k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior DFT Engineer

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The Senior DFT Engineer joins the Design-for-Test Engineering team to develop creative solutions for DFT architecture, verification, and post-silicon validation on complex semiconductor chips. This role involves owning cross-functional projects to implement state-of-the-art designs in test access mechanisms, IO BIST, memory BIST, and scan compression. Key responsibilities include developing DFT methodologies for next-generation products, mentoring junior engineers on test designs, and managing trade-offs regarding cost and quality. Candidates must demonstrate expertise in scan test plans, fault modeling, ATPG, and fault simulation for multi-million gate designs. Required skills include experience with RTL, clocks, STA, place-n-route, and power, alongside silicon debug on ATE. Proficiency in Perl, Python, or Tcl is desired to support verification and validation of test patterns.

Skills

DFT ATPG BIST Scan Compression Fault Modeling Fault Simulation RTL STA Silicon Debug ATE Python Perl Tcl Post-Silicon Validation Verification

What you'll do

Implement state-of-the-art designs for test access mechanisms, IO BIST, memory BIST, and scan compression.
Develop and deploy DFT methodologies for next-generation semiconductor products.
Define scan test plans, BIST for memories and IOs, fault modeling, and ATPG.
Perform verification and validation of test patterns and logic on multi-million gate designs.
Conduct silicon debug and bring-up on ATE including failure processing and test program development.
Mentor junior engineers on test designs and trade-offs regarding cost and quality.
Evaluate cross-functional areas like RTL, clocks, STA, and power to ensure optimal design trade-offs.

What we're looking for

BSEE with experience, MSEE with experience, or a PhD in DFT or related domains.
Demonstrated knowledge and expertise in defining scan test plans, BIST for memories and IOs, fault modeling, ATPG, and fault simulation.
Excellent analytical skills in verification and validation of test patterns and logic on complex, multi-million gate designs using vendor tools.
Good exposure to cross-functional areas including RTL & clocks design, STA, place-n-route, and power.
Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development.
Strong programming and scripting skills in Perl, Python, or Tcl (preferred).
Extraordinary written and oral communication skills.

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