Senior DFT Methodology Engineer

Nvidia

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Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 2 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $200k

This role $216k

$138k most similar roles pay here $278k

This role pays more than 71% of similar roles. Most pay $177,250–$222,000 — the shaded band above. At the midpoint, this role pays about $216k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1391 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1116 roles with salary data.

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At a glance

TL;DR · Senior DFT Methodology Engineer

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As a Senior DFT Methodology Engineer, you will join the Design-for-Test Engineering team to architect and develop test methodologies that ensure next-generation silicon is testable, debuggable, and secure from initial bring-up. You will own and implement state-of-the-art designs in test access mechanisms, I1149.1, I1500, I1687, 1838, memory BIST, memory dump, and DFX security methodology while mentoring junior engineers on trade-offs between cost and quality. You will collaborate with cross-functional teams across RTL design, verification, timing, physical design, software, and production to deploy methodologies for complex semiconductor chips. The role requires expertise in SoC architecture, RTL design, and verification using vendor tools to validate patterns on multi-million-gate designs. Required skills include experience in silicon debug, ATE bring-up, and programming in Perl, Python, or Tcl to solve challenges in advanced semiconductor technologies.

Skills

DFT SoC Architecture RTL Design Verification Memory BIST ATE Python Perl Tcl STA Pattern Generation Silicon Debug DFX

What you'll do

Architect and develop test methodologies to ensure silicon is testable, debuggable, and secure.
Implement state-of-the-art designs in test access mechanisms, memory BIST, and DFX security methodology.
Develop and deploy DFT methodologies for RTL design, verification, and pattern generation.
Partner with cross-functional teams to balance trade-offs between manufacturing cost and product quality.
Use vendor tools to verify and validate test patterns on complex, multi-million-gate designs.
Perform silicon debug and bring-up on ATE while managing failure processing and test program development.
Mentor junior engineers on test designs and technical trade-offs.

What we're looking for

BS/MS in Electrical or Computer Engineering or equivalent experience in a related domain.
10+ years of hands-on experience in SoC architecture, RTL design, and verification.
Experience using vendor tools to verify and validate test patterns and logic on complex, multi-million-gate designs.
Exposure to cross-functional areas including RTL & clocks design, STA, place-n-route, and power.
Experience in silicon debug and bring-up on ATE with understanding of pattern formats and failure processing.
Exceptional written and oral interpersonal skills.
Knowledge of DFT security and hardware system security (preferred).
Strong programming and scripting skills in Perl, Python, or Tcl (preferred).

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