Senior DFT Methodology Engineer

What you'll do

• Architect and develop test methodologies for next-generation silicon to ensure testability, debuggability, and security.
• Implement state-of-the-art designs in test access mechanisms, including I1149.1, I1500, I1687, 1838, and memory BIST.
• Develop and deploy DFT methodologies for RTL design, verification, and pattern generation.
• Partner with timing, physical design, and software teams to balance trade-offs between cost and quality.
• Perform silicon debug and bring-up on ATE using pattern formats and failure processing.
• Mentor junior engineers on test designs, methodology adoption, and technical trade-offs.
• Use vendor tools to verify and validate test patterns and logic on multi-million-gate designs.

What we're looking for

• BS/MS in Electrical or Computer Engineering or equivalent experience in a related domain.
• 10+ years of hands-on experience in SoC architecture, RTL design, and verification.
• Proven experience in DFT methodology, including test access mechanisms, I1149.1, I1500, I1687, 1838, memory BIST, and memory dump.
• Experience in silicon debug and bring-up on ATE with understanding of pattern formats and failure processing.
• Strong analytical skills using vendor tools to verify and validate test patterns on multi-million-gate designs.
• Exposure to cross-functional areas including RTL & clocks design, STA, place-n-route, and power.
• Strong written and oral interpersonal skills.
• Knowledge of DFT security and hardware system security (preferred).
• Strong programming and scripting skills in Perl, Python, or Tcl (preferred).
• Proven track record of deploying advanced DFT methodologies in groundbreaking semiconductor technologies (preferred).
• Experience mentoring engineers and driving methodology adoption (preferred).