DFT Methodology Engineer

Nvidia

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $168,000–$264,500 / yr
Posted: 7 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $184k

This role $216k

$127k most similar roles pay here $279k

This role pays more than 78% of similar roles. Most pay $151,612–$216,062 — the shaded band above. At the midpoint, this role pays about $216k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · DFT Methodology Engineer

Role Posting Log in to save

The DFT Methodology Engineer joins the Design-for-Test Engineering team to develop innovative solutions for DFT architecture, verification, and post-silicon validation on complex semiconductor chips. In this role, you will own cross-functional projects implementing state-of-the-art designs in test access mechanisms, I1149.1, I1500, I1687, 1838, memory BIST, scan, memory dump, and DFX security methodology. You will architect, develop, and deploy DFT methodologies for next-generation products involving RTL design, pattern generation, and collaboration with timing, physical design, software, and bringup teams. The role requires expertise in SoC architecture, RTL design, verification of multi-million gate designs using vendor tools, and silicon debug on ATE. Key skills include understanding STA, place-n-route, power, and hardware system security. You will also mentor junior engineers on test designs while balancing critical trade-offs regarding cost and quality.

Skills

DFT SoC Architecture RTL Design Verification Scan Memory BIST ATE STA Pattern Generation Silicon Debug Bring-up DFX I1149.1 I1500 I1687 1838

What you'll do

Implement state-of-the-art designs in test access mechanisms and memory BIST.
Develop and deploy DFT methodologies for next-generation products including RTL design and verification.
Generate test patterns and manage scan and memory dump processes.
Architect DFX security methodologies for complex semiconductor chips.
Perform silicon debug and bring-up on ATE with an understanding of pattern formats.
Analyze trade-offs between cost, quality, and performance across cross-functional design areas.
Mentor junior engineers on test designs and technical trade-offs.

What we're looking for

Master’s degree in Electrical Engineering or a related field is required.
Proven experience in DFT or related domains is required.
10+ years of hands-on experience in SoC architecture, RTL design, and verification are required.
Experience must include test access mechanisms, I1149.1, I1500, I1687, 1838, memory BIST, scan, and memory dump.
Analytical skills in verification and validation of test patterns on multi-million gate designs using vendor tools are required.
Experience in silicon debug and bring-up on ATE with knowledge of pattern formats and failure processing is required.
Knowledge of DFT security and hardware system security is preferred.
Exceptional written and oral interpersonal skills are required.